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ATSAMD20-XPRO
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Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
z
Nested Vectored Interrupt Controller (NVIC)
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External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low
latency interrupt processing and efficient processing of late arriving interrupts. Refer to
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low
latency interrupt processing and efficient processing of late arriving interrupts. Refer to
and the Cortex-M0+ Technical Reference Manual for details
(
www.arm.com)
.
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System Control Block (SCB)
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The System Control Block provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic
User Guide for details (
configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic
User Guide for details (
www.arm.com)
.
10.1.3 Cortex-M0+ Address Map
Table 10-1. Cortex-M0+ Address Map
10.1.4 I/O Interface
10.1.4.1 Overview
Because accesses to the AMBA AHB-Lite and the single-cycle I/O interface can be made concurrently, the Cortex-M0+
processor can fetch the next instructions while accessing the I/Os. This enables single-cycle I/O accesses to be
sustained for as long as needed.
processor can fetch the next instructions while accessing the I/Os. This enables single-cycle I/O accesses to be
sustained for as long as needed.
10.1.4.2 Description
Direct access to PORT registers.
10.2
Nested Vector Interrupt Controller
10.2.1 Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM D20 supports 32 interrupt lines with four different priority
levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (
levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (
www.arm.com)
.
10.2.2 Interrupt Line Mapping
Each of the 32 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can
have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The
interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request
is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt
requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An
interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers
(SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt
enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority
field for each interrupt.
have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The
interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request
is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt
requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An
interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers
(SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt
enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority
field for each interrupt.
Address
Peripheral
0xE000E000
System Control Space (SCS)
0xE000E010
System Timer (SysTick)
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
0xE000ED00
System Control Block (SCB)