Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Hoja De Datos
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ATSAMD20-XPRO
344
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
rate desired. In this case, the BAUD register value should be selected to give the lowest possible error. Refer to
Recommended maximum receiver baud-rate errors for various character sizes are shown in the table below.
Table 24-2. Asynchronous Receiver Error
The recommended maximum receiver baud-rate error assumes that the receiver and transmitter equally divide the
maximum total error.
maximum total error.
The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate:
where:
z
Dis the sum of character size and parity size (D = 5 to 10 bits)
z
R
SLOW
is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
z
R
FAST
is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
24.6.3 Additional Features
24.6.3.1 Parity
Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit group in the Control A
register (CTRLA.FORM). If even parity is selected by writing a zero to the Parity Mode bit in the Control B register
(CTRLB.PMODE), the parity bit of the outgoing frame is set to one if the number of data bits that are one is odd (making
the total number of ones even). If odd parity is selected by writing a one to CTRLB.PMODE, the parity bit of the outgoing
frame is set to one if the number of data bits that are one is even (making the total number of ones odd).
register (CTRLA.FORM). If even parity is selected by writing a zero to the Parity Mode bit in the Control B register
(CTRLB.PMODE), the parity bit of the outgoing frame is set to one if the number of data bits that are one is odd (making
the total number of ones even). If odd parity is selected by writing a one to CTRLB.PMODE, the parity bit of the outgoing
frame is set to one if the number of data bits that are one is even (making the total number of ones odd).
When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in the
Status register (STATUS.PERR) is set.
compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in the
Status register (STATUS.PERR) is set.
24.6.3.2 Loop-back Mode
By configuring the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO) to use the same data
pins for transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available
externally.
pins for transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available
externally.
D
(Data bits + Parity)
(Data bits + Parity)
R
SLOW
(%)
R
FAST
(%)
Max Total Error (%)
Recommended Max
Rx Error (%)
Rx Error (%)
5
94.12
107.69
+5.88/-7.69
±2.5
6
94.92
106.67
+5.08/-6.67
±2.0
7
95.52
105.88
+4.48/-5.88
±2.0
8
96.00
105.26
+4.00/-5.26
±2.0
9
96.39
104.76
+3.61/-4.76
±1.5
10
96.70
104.35
+3.30/-4.35
±1.5
6
)
1
(
16
)
1
(
16
+
+
+
=
D
D
R
SLOW
8
)
1
(
16
)
2
(
16
+
+
+
=
D
D
R
FAST