Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Hoja De Datos
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ATSAMD20-XPRO
454
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
27.8.2 Read Request
For a detailed description of this register and its use, refer to the
.
Name:
READREQ
Offset:
0x02
Reset:
0x0000
Property:
-
z
Bit 15 – RREQ: Read Request
Writing a zero to this bit has no effect.
Writing a zero to this bit has no effect.
This bit will always read as zero.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READ-
REQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
REQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
z
Bit 14 – RCONT: Read Continuously
0: Continuous synchronization is disabled.
0: Continuous synchronization is disabled.
1: Continuous synchronization is enabled.
When continuous synchronization is enabled, the register pointed to by the Address bit group (READREQ.ADDR)
will be synchronized automatically every time the register is updated.
will be synchronized automatically every time the register is updated.
z
Bits 13:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 4:0 – ADDR[4:0]: Address
These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are
available for read synchronization.
These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are
available for read synchronization.
Bit
15
14
13
12
11
10
9
8
RREQ
RCONT
Access
W
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ADDR[4:0]
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0