Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Hoja De Datos
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ATSAMD20-XPRO
549
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
30.8.1 Control A
Name:
CTRLA
Offset:
0x0
Reset:
0x00
Property:
Write-Protected, Write-Synchronized
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – RUNSTDBY: Run in Standby
0: The DAC output buffer is disabled in standby sleep mode.
1: The DAC output buffer can be enabled in standby sleep mode.
0: The DAC output buffer is disabled in standby sleep mode.
1: The DAC output buffer can be enabled in standby sleep mode.
This bit is not synchronized.
z
Bit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY is cleared when the operation is complete.
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY is cleared when the operation is complete.
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets the all registers in the DAC to their initial state, and the DAC will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write oper-
ation will be discarded.
ation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and STATUS.SYNCBUSY will both be cleared when the reset is complete.
and STATUS.SYNCBUSY will both be cleared when the reset is complete.
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
ENABLE
SWRST
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0