Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Hoja De Datos
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ATSAMD20-XPRO
619
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
35.
Errata
35.1
Revision D
35.1.1 NVMCTRL
1 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the on-
chip flash size minus half a row. Errata reference: 11988
none, the CRC32 is not executed on the entire flash area but up to the on-
chip flash size minus half a row. Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
35.1.2 Device
1 - After a clock failure detection (INTFLAG.CFD = 1), if INTFLAG.CFD is
cleared while the clock is still broken, the system is stuck. Errata reference:
12687
cleared while the clock is still broken, the system is stuck. Errata reference:
12687
Fix/Workaround:
After a clock failure detection, do not clear INTFLAG.CFD or perform a system
reset.
reset.
2 - Clock Failure detection for external OSC does not work in standby mode.
Errata reference: 12688
Errata reference: 12688
Fix/Workaround:
Before entering standby mode, move the CPU clock to an internal RC, disable
external OSC and disable the Clock Failure detector. Upon CPU wakeup, restart
external OSC (if it does not start, the failure occurred during standby), enable the
Clock Failure detector and move the CPU clock to the external OSC.
external OSC and disable the Clock Failure detector. Upon CPU wakeup, restart
external OSC (if it does not start, the failure occurred during standby), enable the
Clock Failure detector and move the CPU clock to the external OSC.
3 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
4 - Digital pin outputs from Timer/Counters, AC (Analog Comparator), GCLK
(Generic Clock Controller), and SERCOM (I2C and SPI) do not change value
during standby sleep mode. Errata reference: 12537
(Generic Clock Controller), and SERCOM (I2C and SPI) do not change value
during standby sleep mode. Errata reference: 12537
Fix/Workaround: