Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Hoja De Datos
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ATSAMD20-XPRO
81
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
14.5.4 Interrupts
Not applicable.
14.5.5 Events
Not applicable.
14.5.6 Debug Operation
Not applicable.
14.5.7 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC).
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode or the CPU reset is extended, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to
14.5.8 Analog Connections
Not applicable.
14.6
Functional Description
14.6.1 Principle of Operation
The GCLK module is comprised of eight generic clock generators sourcing m generic clock multiplexers.
A clock source selected as input to one of the generic clock generators can be used directly, or it can be prescaled in the
generic clock generator before the generator output is used as input to one or more of the generic clock multiplexers.
generic clock generator before the generator output is used as input to one or more of the generic clock multiplexers.
A generic clock multiplexer provides a generic clock to a peripheral (GCLK_PERIPHERAL). A generic clock can act as
the clock to one or several of peripherals.
the clock to one or several of peripherals.
14.6.2 Basic Operation
14.6.2.1 Initialization
Before a generic clock is enabled, the clock source of its generic clock generator should be enabled. The generic clock
must be configured as outlined by the following steps:
must be configured as outlined by the following steps:
1.
The generic clock generator division factor must be set by performing a single 32-bit write to the Generic Clock
Generator Division register (GENDIV):
Generator Division register (GENDIV):
z
The generic clock generator that will be selected as the source of the generic clock must be written to the ID
bit group (GENDIV.ID).
bit group (GENDIV.ID).
z
The division factor must be written to the DIV bit group (GENDIV.DIV)
Refer to
register for details.
2.
The generic clock generator must be enabled by performing a single 32-bit write to the Generic Clock Generator
Control register (GENCTRL):
Control register (GENCTRL):
z
The generic clock generator that will be selected as the source of the generic clock must be written to the ID
bit group (GENCTRL.ID)
bit group (GENCTRL.ID)
z
The generic clock generator must be enabled by writing a one to the GENEN bit (GENCTRL.GENEN)
Refer to
3.
The generic clock must be configured by performing a single 16-bit write to the Generic Clock Control register
(CLKCTRL):
(CLKCTRL):