Linear Technology DC1245A - LTM4616EV | Low Voltage Dual 8A or Single 16A μModule Regulator DC1245A DC1245A Hoja De Datos

Los códigos de productos

DC1245A

LTM4616

4616ff

For more information

www.linear.com/LTM4616

PLLLPF1 and PLLLPF2 (E6 and L6): Phase-Locked Loop

Lowpass Filter for Each Channel. An internal lowpass filter

is tied to this pin. In spread spectrum mode, placing a

capacitor here to SGND controls the slew rate from one

frequency to the next. Alternatively, floating this pin allows

normal running frequency at 1.5MHz, tying this pin to SV

forces the part to run at 1.33 times its normal frequency

(2MHz), tying it to ground forces the frequency to run at

0.67 times its normal frequency (1MHz).
PHMODE1 and PHMODE2 (A9 and G9): Phase Selector

Input for Each Channel. This pin determines the phase

relationship between the internal oscillator and CLKOUT.

Tie it high for 2-phase operation, tie it low for 3-phase

operation, and float or tie it to V

/2 for 4-phase operation.

MGN1 and MGN2 (A10 and G10): Voltage Margining

Pin for Each Channel. Increases or decreases the output

voltage by the amount specified by the BSEL pin. To

disable margining, tie the MGN pin to a voltage divider

with 50k resistors from V

to ground (see Figure 5).

For margining, connect a voltage divider from V

to GND

with the center point connected to the MGN pin for the spe-

cific channel. Each resistor should be close to 50k. Margin

High is within 0.3V of V

, and Margin Low is within 0.3V of

GND. See the Applications Information section and Figure

18 for margining control. The specified tri-state drivers are

capable of the high and low requirements for margining.
BSEL1 and BSEL2 (A6 and G6): Margining Bit Select Pin

for Each Channel. Tying BSEL low selects ±5% margin

value, tying it high selects 10% margin value. Floating it

or tying it to V

/2 selects 15% margin value.

TRACK1 and TRACK2 (E8 and L8): Output Voltage Tracking

Pin for Each Channel. Voltage tracking is enabled when the

TRACK voltage is below 0.57V. If tracking is not desired,

then connect the TRACK pin to SV

. If TRACK is not tied

to SV

, then the TRACK pin’s voltage needs to be below

0.18V before the chip shuts down even though RUN is

IN1

, V

IN2

(BANK1 and BANK2); (F1-F4, E1-E4, C1-C2,

D1-D2) and (J1-J2, K1-K2, L1-L4, M1-M4): Power Input

Pins. Apply input voltage between these pins and GND

pins. Recommend placing input decoupling capacitance

directly between V

pins and GND pins.

OUT1

OUT2

(BANK3 and BANK6); (D9-D12, E9-E12,

F9-F12) and (K9-K12, L9-L12, M9-M12): Power Output

Pins. Apply output load between these pins and GND

pins. Recommend placing output decoupling capacitance

directly between these pins and GND pins. See Table 1.
GND1 and GND2 (BANK2 and BANK5); (A1-A5, A12, B1-

B5, B7-B12, C3-C12, D3-D7) and (G1-G5, G12, H1-H5,

H7-H12, J3-J12, K3-K7): Power Ground Pins for Both

Input and Output Returns.
SV

IN1

and SV

IN2

(E5 and L5): Signal Input Voltage for Each

Channel. This pin is internally connected to V

through

a lowpass filter.
SGND1 and SGND2 (F5 and M5): Signal Ground Pin for

Each Channel. Return ground path for all analog and low

power circuitry. Tie a single connection to the output

capacitor GND in the application. See layout guidelines

in Figure 17.
MODE1 and MODE2 (A8 and G8): Mode Select Input for

Each Channel. Tying this pin high enables Burst Mode

operation. Tying this pin low enables forced continuous

operation. Floating this pin or tying it to V

/2 enables

pulse-skipping operation.
CLKIN1 and CLKIN2 (A7 and G7): External Synchroniza-

tion Input to Phase Detector for Each Channel. This pin

is internally terminated to SGND with a 50k resistor. The

phase-locked loop will force the internal top power PMOS

turn on to be synchronized with the rising edge of the

CLKIN signal. Connect this pin to SV

to enable spread

spectrum modulation. During external synchronization,

make sure the PLLLPF pin is not tied to V

or GND.

pin Functions