Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Hoja De Datos
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ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
1172
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive Start Delay) and START = 4, or 5 or
7(Receive Start Selection), two periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabilization.
illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4, and SSC7, SSC10 and SSC13.
3. 1.8V domain: V
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 20 pF.
4. 3.3V domain: V
VDDIO
from 2.85V to 3.6V, maximum external capacitor = 30 pF.
Figure 44-30. Min and Max Access Time of Output Signals
SSC
TK Edge to TF/TD (TK Input, TF Input)
1.8V domain
3.3V domain
4.5(+3*t
CPMCK)
3.8(+3*t
CPMCK)
16.3(+3*t
CPMCK)
13.3(+3*t
CPMCK)
ns
Receiver
SSC
8
RF/RD Setup Time before RK Edge (RK Input)
1.8V domain
3.3V domain
0
—
ns
SSC
9
RF/RD Hold Time after RK Edge (RK Input)
1.8V domain
3.3V domain
t
CPMCK
—
ns
SSC
10
RK Edge to RF (RK Input)
1.8V domain
3.3V domain
4.7
4
16.1
12.8
12.8
ns
SSC
11
RF/RD Setup Time before RK Edge (RK Output)
1.8V domain
3.3V domain
15.8 - t
CPMCK
12.5- t
CPMCK
—
ns
SSC
12
RF/RD Hold Time after RK Edge (RK Output)
1.8V domain
3.3V domain
t
CPMCK
- 4.3
t
CPMCK
- 3.6
—
ns
SSC
13
RK Edge to RF (RK Output)
1.8V domain
3.3V domain
-3
-2.6
4.3
3.8
3.8
ns
Table 44-64.
SSC Timings (Continued)
Symbol
Parameter
Condition
Min
Max
Units
TK (CKI =0)
TF/TD
SSC
0min
TK (CKI =1)
SSC
0max