Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Hoja De Datos
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ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
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the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is
defined in the CPOL bit of the PWM_CMRx. By default the signal starts by a low level.
the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can
be used to generate non overlapped waveforms. This property is defined in the CALG bit of the
PWM_CMRx. The default mode is left aligned.
Figure 39-4.
Non Overlapped Center Aligned Waveforms
Note:
for a detailed description of center aligned waveforms.
When center aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period.
When left aligned, the channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned
When left aligned, the channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned
channel.
Waveforms are fixed at 0 when:
Waveforms are fixed at 0 when:
CDTY = CPRD and CPOL = 0
CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
CDTY = 0 and CPOL = 0
CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level.
Modifying CPOL in
Modifying CPOL in
while the channel is enabled can lead to an unexpected
behavior of the device being driven by PWM.
Besides generating output signals OCx, the comparator generates interrupts in function of the counter value.
Besides generating output signals OCx, the comparator generates interrupts in function of the counter value.
When the output waveform is left aligned, the interrupt occurs at the end of the counter period. When the output
waveform is center aligned, the bit CES of the PWM_CMRx defines when the channel counter interrupt occurs. If
CES is set to ‘0’, the interrupt occurs at the end of the counter period. If CES is set to ‘1’, the interrupt occurs at the
end of the counter period and at half of the counter period.
illustrates the counter interrupts in function of the configuration.
OC0
OC1
Period
No overlap