Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Hoja De Datos
Los códigos de productos
ATSAM4L-XSTK
319
42023E–SAM–07/2013
ATSAM4L8/L4/L2
16.3
Block Diagram
Figure 16-1. PDCA Block Diagram
16.4
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
below.
16.4.1
Power Management
If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning
and resume operation after the system wakes up from sleep mode.
and resume operation after the system wakes up from sleep mode.
16.4.2
Clocks
The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and
one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Man-
ager. The status of both clocks at reset can be known in the Power Manager section. It is
recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in
an undefined state.
one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Man-
ager. The status of both clocks at reset can be known in the Power Manager section. It is
recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in
an undefined state.
16.4.3
Interrupts
The PDCA interrupt request lines are connected to the NVIC. Using the PDCA interrupts
requires the NVIC to be programmed first.
requires the NVIC to be programmed first.
HSB to PB
Bridge
Peripheral DMA
Controller
(PDCA)
Peripheral
0
High Speed
Bus Matrix
Handshake Interfaces
Pe
ri
ph
er
al Bus
IRQ
HSB
HSB
Interrupt
Controller
Peripheral
1
Peripheral
2
Peripheral
(n-1)
..
.
Memory
HSB