Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Hoja De Datos
Los códigos de productos
ATSAM4L-XSTK
751
42023E–SAM–07/2013
ATSAM4L8/L4/L2
The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one.
See
See
Figure 28-7. Slave Transmitter with One Data Byte
Figure 28-8. Slave Transmitter with Multiple Data Bytes
Figure 28-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF
28.8.5
Slave Receiver Mode
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is
cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one
CLK_TWIS cycle after the relevant address match bit in the same register is set).
cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one
CLK_TWIS cycle after the relevant address match bit in the same register is set).
After the address phase, the following is repeated:
TCOMP
TXRDY
Write THR (DATA)
STOP sent by master
TWD
A
DATA
N
S
DADR
R
P
NBYTES set to 1
A
DATA n
A
S
DADR
R
DATA n+5
A
P
DATA n+m
N
TCOMP
TXRDY
Write THR (Data n)
NBYTES set to m
STOP sent by master
TWD
Write THR (Data n+1)
Write THR (Data n+m)
Last data sent
DATA (LSB)
N
P
TWCK
SR.NAK
SR.BTF
t
1
t
1
t
1
: (CLK_TWIS period) x 2
TWD