Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Hoja De Datos

42023E–SAM–07/2013

(CR.DIS). Another way to reset ADCIFE is to write a one in the SWRST field of the Control Reg-
ister (CR.SWRST). In both cases configuration registers won’t be affected.

Refer to 

The ADC allows the possibility to select several voltage reference (Vref).

• An internal 1.0V voltage reference derived from the internal 1.1V

• 0.625*Vcc (to get 1.0V when Vcc=1.6V)

• Vcc/2

• 2 external reference inputs

The ADC cell allows to affect different gain for each conversion by configuring approprietely the
Gain Factor field GAIN in the SEQCFG register.

The programmable input amplification is from 1x to 64x. Moreover, this amplification can be
divided by 2 by setting all bits in the field GAIN in the SEQCFG register to seven.

If the Half Word Left Adjust (HWLA) bit in the SEQCFG register is set, then the result will be left
adjusted on the 16 lower bits of the LCV register. Otherwise, results will be right-adjusted.

Positive and negative channels used in the last conversion are available both by reading the
Sequencer Last Converted Value register (LCV).

Operating modes description

Differential 
mode without 
gain

-Vref to + Vref

0 to 4095 (11 bits signed
number)

6 clock_cycles

2047 + (Vin/Vref)*2047

Differential 
mode with 
gain=2n

-Vref/2

n

 to 

+Vref/2

n

 0 to 4095 (11 bits signed
number)

7 clock_cycles for
n=1 (gain=2)

9 clock_cycles for
n=6 (gain=64)

2047 + (2

n

*Vin/Vref)*2047

Differential 
mode with divi-
sion by 2

-2*Vref to 
+2*Vref

 0 to 4095 (11 bits signed
number)

7 clock_cycles

2047 + (Vin/(2*Vref))*2047

Differential 
mode with zoom 
and gain =2n  
(n>0)

-Vref/2n+Vshift, 
Vref/2n+Vshift

Vshift=Vsup(1/4*
z o o m -
range[1]+1/8*zo
omrange[0])

 0 to 4095 (11 bits signed
number)

7 clock_cycles for
n=1 (gain=2)

10 clock_cycles
for n=6 (gain=64)

2 0 4 7 + ( 2

n

* ( V i n -

Vshift)/Vref*2047