Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Hoja De Datos
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ATSAMD21-XPRO
835
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
32.5.10 Calibration
The values BIAS_CAL and LINEARITY_CAL from the production test must be loaded from the NVM Software Calibration
Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy.
Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy.
for more details.
32.6 Functional Description
32.6.1 Principle of Operation
By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order to reduce the
conversion time. The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The
input values can be either internal (e.g., internal temperature sensor) or external (connected I/O pins). The user can also
configure whether the conversion should be single-ended or differential.
conversion time. The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The
input values can be either internal (e.g., internal temperature sensor) or external (connected I/O pins). The user can also
configure whether the conversion should be single-ended or differential.
32.6.2 Basic Operation
32.6.2.1 Initialization
Before enabling the ADC, the asynchronous clock source must be selected and enabled, and the ADC reference must be
configured. The first conversion after the reference is changed must not be used. All other configuration registers must
be stable during the conversion. The source for GCLK_ADC is selected and enabled in the System Controller
(SYSCTRL). Refer to
configured. The first conversion after the reference is changed must not be used. All other configuration registers must
be stable during the conversion. The source for GCLK_ADC is selected and enabled in the System Controller
(SYSCTRL). Refer to
for more details.
When GCLK_ADC is enabled, the ADC can be enabled by writing a one to the Enable bit in the Control Register A
(CTRLA.ENABLE).
(CTRLA.ENABLE).
32.6.2.2 Enabling, Disabling and Reset
The ADC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The ADC is disabled
by writing a zero to CTRLA.ENABLE.
by writing a zero to CTRLA.ENABLE.
The ADC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the
ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled. Refer to the
ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled. Refer to the
details.
The ADC must be disabled before it is reset.
32.6.2.3 Basic Operation
In the most basic configuration, the ADC sample values from the configured internal or external sources (
register). The rate of the conversion is dependent on the combination of the GCLK_ADC frequency and the clock
prescaler.
prescaler.
To convert analog values to digital values, the ADC needs first to be initialized, as described in
. Data conversion can be started either manually, by writing a one to the Start bit in the Software Trigger register
(SWTRIG.START), or automatically, by configuring an automatic trigger to initiate the conversions. A free-running mode
could be used to continuously convert an input channel. There is no need for a trigger to start the conversion. It will start
automatically at the end of previous conversion.
could be used to continuously convert an input channel. There is no need for a trigger to start the conversion. It will start
automatically at the end of previous conversion.
The automatic trigger can be configured to trigger on many different conditions.
The result of the conversion is stored in the Result register (
) as it becomes available, overwriting the result from
the previous conversion.
To avoid data loss if more than one channel is enabled, the conversion result must be read as it becomes available
(INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the
Interrupt Flag Status and Clear register (INTFLAG.OVERRUN).
(INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the
Interrupt Flag Status and Clear register (INTFLAG.OVERRUN).
To use an interrupt handler, the corresponding bit in the Interrupt Enable Set register (INTENSET) must be written to
one.
one.