Linear Technology DC1096-A LTC2642 16-Bit Unbuffered VOUT DAC DC1096A DC1096A Hoja De Datos
Los códigos de productos
DC1096A
LTC2641/LTC2642
5
26412fc
For more information
www.linear.com/LTC2641
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full
Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full
scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale.
LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale.
elecTrical characTerisTics
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V or 5V, V
REF
= 2.5V, C
L
= 10pF, GND = 0, R
L
= ∞
unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
IN
Digital Input Current
V
IN
= GND to V
DD
l
±1
µA
C
IN
Digital Input Capacitance
(Note 6)
l
3
10
pF
V
H
Hysteresis Voltage
0.15
V
Power Supply
V
V
DD
Supply Voltage
l
2.7
5.5
V
I
DD
Supply Current, V
DD
Digital Inputs = 0V or V
DD
l
120
200
µA
P
D
Power Dissipation
Digital Inputs = 0V or V
DD
, V
DD
= 5V
Digital Inputs = 0V or V
DD
, V
DD
= 3V
0.60
0.36
mW
mW
TiMing characTerisTics
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V or 5V, V
REF
= 2.5V, C
L
= 10pF, GND = 0, R
L
= ∞
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
1
DIN Valid to SCLK Setup Time
l
10
ns
t
2
DIN Valid to SCLK Hold Time
l
0
ns
t
3
SCLK Pulse Width High
l
9
ns
t
4
SCLK Pulse Width Low
l
9
ns
t
5
CS Pulse High Width
l
10
ns
t
6
LSB SCLK High to CS High
l
8
ns
t
7
CS Low to SCLK High
l
8
ns
t
8
CS High to SCLK Positive Edge
l
8
ns
t
9
CLR Pulse Width Low
l
15
ns
f
SCLK
SCLK Frequency
50% Duty Cycle
l
50
MHz
V
DD
High to CS Low (Power-Up Delay)
30
µs
Note 4: R
OUT
tolerance is typically ±20%.
Note 5: Reference input resistance is code dependent. Minimum is at
871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar
mode.
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
tested.