STMicroelectronics Stepper motor driver mounting the L6474 in high power PowerSO package EVAL6474PD EVAL6474PD Hoja De Datos
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EVAL6474PD
Pin connection
L6474
16/52
Doc ID 022529 Rev 3
4.1 Pin
list
Table 6.
Pin description
N. Name
Type
Function
17
VDD
Power
Logic outputs supply voltage (pull-up reference)
6 VREG
Power
Internal 3 V voltage regulator output and 3.3 V external logic
supply
supply
7 OSCIN Analog
input
Oscillator pin 1. To connect an external oscillator or clock source.
If this pin is unused, it should be left floating.
If this pin is unused, it should be left floating.
8 OSCOUT Analog
output
Oscillator pin 2. To connect an external oscillator. When the
internal oscillator is used this pin can supply 2/4/8/16 MHz. If this
pin is unused, it should be left floating.
internal oscillator is used this pin can supply 2/4/8/16 MHz. If this
pin is unused, it should be left floating.
10
CP
Output
Charge pump oscillator output
11 VBOOT Supply
voltage
Bootstrap voltage needed for driving the high-side power DMOS of
both bridges (A and B)
both bridges (A and B)
5
ADCIN
Analog input
Internal analog to digital converter input
2
VSA
Power supply
Full-bridge A power supply pin. It must be connected to VSB
26
12
VSB
Power supply
Full-bridge B power supply pin. It must be connected to VSA
16
27
PGND Ground
Power
ground
pin
13
1
OUT1A
Power output
Full-bridge A output 1
28
OUT2A
Power output
Full-bridge A output 2
14
OUT1B
Power output
Full-bridge B output 1
15
OUT2B
Power output
Full-bridge B output 2
9 AGND
Ground
Analog
ground
4
DIR
Logical input
Direction input
21 DGND
Ground Digital
ground
22
SYNC
Open drain output Synchronization signal.
18
SDO
Logic output
Data output pin for serial interface
20
SDI
Logic input
Data input pin for serial interface
19
CK
Logic input
Serial interface clock
23 CS
Logic input
Chip select input pin for serial interface
24 FLAG
Open drain output
Status flag pin. An internal open drain transistor can pull the pin to
GND when a programmed alarm condition occurs (step loss,
OCD, thermal pre-warning or shutdown, UVLO, wrong command,
non performable command)
GND when a programmed alarm condition occurs (step loss,
OCD, thermal pre-warning or shutdown, UVLO, wrong command,
non performable command)
3 STBY\RST Logic input
Standby and reset pin. LOW logic level resets the logic and puts
the device into standby mode. If not used, should be connected to
VDD
the device into standby mode. If not used, should be connected to
VDD