Intel S5500WBR Manual De Usuario
Functional Architecture
Intel® Server Board S5500WB TPS
22
Revision 1.9
Intel order number E53971-008
The memory channels from socket 1 are identified as Channels A, B, and C. The memory
channels from socket 2 are identified as Channels D, E, and F.
channels from socket 2 are identified as Channels D, E, and F.
The DIMM identifiers on the silkscreen on the board provide information about the channel,
and, therefore the processor, to which they belong. For example, DIMM_A1 is the first slot on
Channel A on processor 1; DIMM_D1 is the first DIMM socket on Channel D on processor 2.
and, therefore the processor, to which they belong. For example, DIMM_A1 is the first slot on
Channel A on processor 1; DIMM_D1 is the first DIMM socket on Channel D on processor 2.
Table 5. DIMM Nomenclature
Processor Socket 1
Processor Socket 2
Channel A
Channel B
Channel C
Channel D
Channel E
Channel F
A1
A2
B1
C1
D1
D2
E1
F1
If the socket is not populated, the memory slots associated with a processor socket
are unavailable.
are unavailable.
You can install a processor without populating the associated memory slots provided a second
processor is installed with associated memory. In this case, the memory is shared by the
processors. However, the platform suffers performance degradation and latency due to the
remote memory.
processor is installed with associated memory. In this case, the memory is shared by the
processors. However, the platform suffers performance degradation and latency due to the
remote memory.
Sockets are self-contained and autonomous. However, all configurations in the BIOS setup
such as RAS, Error Management, and so forth, are applied commonly across sockets.
such as RAS, Error Management, and so forth, are applied commonly across sockets.
3.4.3
ECC Support
If at least one non-ECC DIMM is present in the system, the system reverts to non-ECC mode.
UDIMMs can be ECC or non-ECC; RDIMMs are always ECC enabled. Non-ECC DIMMs are not
validated and not recommended for server use.
UDIMMs can be ECC or non-ECC; RDIMMs are always ECC enabled. Non-ECC DIMMs are not
validated and not recommended for server use.
3.4.4
Memory Reservation for Memory-mapped Functions
A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset,
processor, and BIOS (flash) memory-mapped I/O regions. This region displays as a loss of
memory to the operating system. In addition to this loss, the BIOS creates another reserved
region for memory-mapped PCI Express* functions, including a standard 64 MB or 256 MB of
standard PCI Express* Memory Mapped I/O (MMIO) configuration space. This is based on the
setup selection using the MAX_BUS_NUMBER feature offered by Intel
processor, and BIOS (flash) memory-mapped I/O regions. This region displays as a loss of
memory to the operating system. In addition to this loss, the BIOS creates another reserved
region for memory-mapped PCI Express* functions, including a standard 64 MB or 256 MB of
standard PCI Express* Memory Mapped I/O (MMIO) configuration space. This is based on the
setup selection using the MAX_BUS_NUMBER feature offered by Intel
®
Tylersburg IOH chipset
and a variably sized MMIO region for the PCI Express* functions.
All these reserved regions are reclaimed by the operating system if Physical Address Extension
(PAE) is turned on in the operating system.
All these reserved regions are reclaimed by the operating system if Physical Address Extension
(PAE) is turned on in the operating system.
3.4.5
High-Memory Reclaim
When 4 GB or more of physical memory is installed (physical memory is the memory installed
as DDR3 DIMMs), the reserved memory is lost. However, the Intel
as DDR3 DIMMs), the reserved memory is lost. However, the Intel
®
5500 Series Chipset
provides a feature called high-memory reclaim, which allows the BIOS and operating system to
remap the lost physical memory into system memory above 4 GB (the system memory is the
memory that can be seen by the processor).
remap the lost physical memory into system memory above 4 GB (the system memory is the
memory that can be seen by the processor).