Intel S5500WBR Manual De Usuario
Platform Management Features
Intel® Server Board S5500WB TPS
Revision 1.9
Intel order number E53971-008
44
5.6 I2C\SMBUS Architecture Block
Figure 20.
S5500WB I2C\SMBUS Block Diagram
5.6.1
I2C\SMBUS Device Addresses
Table 21 lists the I2C\SMBus addresses of various devices by bus.
Table 16. I2C/SMBus Device Address Assignment
Main
Bus
Power
Rail
Sub
Bus
Power
Rail
Device
I2C\SMBus
Address
Note
Host
3V3SB
NA
NA
IBMC I2C\SMBus 3
No Connect
ICH10R SMBus
0x88
CK509B
0xD2
DB403
0xDC
Host
3V3
XDP
DB803
0xDC
CPU0 DIMM 1A
0xA0
CPU0 DIMM 2A
0xA2
CPU0 DIMM 1B
0xA4
CPU0 DIMM 1C
0xA6
CPU0 DIMM 1D
0xA8
CPU0 DIMM 2D
0xAA
CPU0 DIMM 1E
0xAC
CPU0 DIMM 1F
0xAE
Sensor
3V3SB
NA
NA
IBMC I2C\SMBus 1
Temp Sensor
0x9E
FP Temp Sensor
0x9A
FP FRU
0xAE
Baseboard FRU
0xA8
CPU IOH
0xE0
IPMI
3V3SB
NA
NA
IBMC I2C\SMBus 0
IPMI
5VSB
IPMI Connector
IPMI
5V
HSBP A
0xC0