Intel III Xeon 667 MHz 80526KZ667256 Hoja De Datos
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80526KZ667256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
19
Table 6. Current Specifications
1,10
Symbol
Parameter
Min
Typ
Max
Unit
Notes
ICCTAP
ICC for TAP power
supply
100
mA
ICCSMBus
ICC for SMBus power
supply
3
22.5
mA
8
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies. “FMB” is a suggested design guideline for
flexible motherboard design.
flexible motherboard design.
2.
VCC_core/Icc_core supplies the processor core, integrated L2 cache and OCVR.
3.
Max I
CC
measurements are measured at V
CC
minimum voltage under maximum signal loading conditions.
4.
This is the current required for a single Pentium® III Xeon™ processor at 600 MHz+. A similar current is drawn through the
termination resistors of each load on the AGTL+ bus. V
termination resistors of each load on the AGTL+ bus. V
TT
is decoupled on the SC330 cartridge such that negative current flow due to
the active pull-up to
VCC_CORE
in the Pentium III Xeon processor at 600 MHz+ will not be seen at the processor fingers.
5.
The current specified is also for AutoHALT state.
6.
These maximum values are specified by design/characterization at nominal V
CC
and at the SC330 edge fingers.
7.
Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance tolerable
and reaction time of the voltage regulator. This parameter is not tested.
and reaction time of the voltage regulator. This parameter is not tested.
8.
VCC_SMB must be connected to 3.3V power supply (even if the SMBus features are not used) in order for the Pentium® III Xeon™
processor at 600 MHz+ to function properly.
processor at 600 MHz+ to function properly.
9.
A disabled Pentium III Xeon processor at 600 MHz+ OCVR draws approximately 46 mA load at 2.8V VCC
_
CORE
from the motherboard
VRM. If your system needs to maintain VRM regulation with a disabled Pentium III Xeon processor at 600 MHz+ (OCVR_EN
inactive), the VRM output minimum load specification should be 46 mA or less.
inactive), the VRM output minimum load specification should be 46 mA or less.
10. The FMB specification is applicable to 2.8V OCVR processors where a VRM is used as the power source.
Table 7. AGTL+ Signal Groups, DC Specifications at the processor Core
Symbol
Parameter
Min
Max
Unit
Notes
V
IL
Input Low Voltage
-0.150
2/3 VTT –
0.2V
V
4,7
V
IH
Input High Voltage
2/3 V
TT
+0.2V
V
TT
V
1,4,7
R
ONN
nMOS On Resistance
16.67
Ohm
5, 6
R
ONP
pMOS On Resistance
85
Ohm
5, 8
V
OHTS
Output High Voltage Tri-state
V
TT
V
1, 4
I
L
Leakage current for the Inputs,
Outputs and I/O
Outputs and I/O
±15
µA
2, 3
NOTES:
1.
Processor core parameter correlated into a 50-ohm resistor to a V
TT
of 1.5V for Pentium III Xeon processor at 600 MHz+.
2.
0
≤
Vin
≤
1.5 +3%.
3.
0
≤
Vout
≤
2 +5%.
4.
The processor core drives high for only one clock cycle. It then drives low or tri-states its outputs. V
TT
is specified in Table 5.
5.
Not 100% tested. Specified by design characterization.
6.
This R
ON
specification corresponds to a V
OL_MAX
of 0.3V when taken into an effective 50-ohm load to V
TT
of 1.5V for Pentium III
Xeon processor at 600 MHz+.
7.
Vil/Vih are not guaranteed with respect to AC parameters.
8.
Specified under no load conditions at an I-V operating point of zero current and V=VTT conditions.