Intel 1.40 GHz RH80532NC017256 Hoja De Datos
Los códigos de productos
RH80532NC017256
Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
62 Datasheet
298517-006
Table 40. Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core
Allowed Pulse Duration (ns) [Tj=100C (see note 6)]
Max V
Cmos
+ Overshoot/Undershoot
Magnitude
(volts)
Activity Factor = 0.01 Activity Factor = 0.1 Activity Factor = 1
2.38 6.5
0.65
0.065
2.33
13
1.3
0.13
2.28 29
2.9
0.29
2.23 60
6
0.6
2.18 60
12
1.2
2.13 60
26
2.6
2.08 60
56
5.6
NOTES:
1. V
CMOS
(nominal) = 1.5 V.
2. Under no circumstances should the sum of the Max V
CMOS
and absolute value of the Overshoot/Undershoot
voltage exceed 2.38 V.
3. Activity factor of 1 represents a toggle rate of 33 MHz.
4. System designers are encouraged to follow Intel provided non-AGTL layout guidelines.
5. All values are specified by design characterization, and are not tested.
6. Tj = 85
4. System designers are encouraged to follow Intel provided non-AGTL layout guidelines.
5. All values are specified by design characterization, and are not tested.
6. Tj = 85
°C for 1.33 GHz.
4.3.1 PWRGOOD,
VTTPWRGD
Signal Quality Specifications
The processor requires PWRGOOD to be a clean indication that clocks and the power supplies (V
CC
,
V
CCT
, etc.) are stable and within their specifications. Clean implies that the signal will remain below
V
IL18
and without errors from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (1.8 V) state. The VTTPWRGD
signal must also transition monotonically.
signal must also transition monotonically.
The VTTPWRGD signal is an input to the processor used to determine that the VTT power is stable and
the VID and BSEL signals should be driven to their final state by the processor. To ensure the processor
correctly reads this signal, the processor must meet the requirement shown in Table 41 while the signal
is in its transition region of 300 mV to 900 mV. Also, VTTPWRGD should only enter the transition
region once, after VTT is at nominal values, for the assertion of the signal.
the VID and BSEL signals should be driven to their final state by the processor. To ensure the processor
correctly reads this signal, the processor must meet the requirement shown in Table 41 while the signal
is in its transition region of 300 mV to 900 mV. Also, VTTPWRGD should only enter the transition
region once, after VTT is at nominal values, for the assertion of the signal.
4.3.1.1
VTTPWRGD Noise Parameter Specification
Table 41. VTTPWRGD Noise Parameter Specification
Parameter Specification
Amount of noise (glitch)
Less than 100 mV
In addition, the VTTPWRGD signal should have reasonable transition time through the transition region.
A sharp edge on the signal transition will minimize the chance of noise causing a glitch on this signal.
Intel recommends the following transition time for the VTTPWRGD signal.