Intel 1.80 GHz RH80532NC033256 Hoja De Datos
Los códigos de productos
RH80532NC033256
Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
46 Datasheet
298517-006
Table 31. Reset Configuration AC Specifications and Power On/Power Down Timings
Symbol Parameter Min Typ Max
Unit
Figure
Notes
T16
Reset Configuration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0) Setup
Time
BREQ0#, FLUSH#, INIT#, PICD0) Setup
Time
4 BCLKs 11
Before deassertion of
RESET#
RESET#
T17
Reset Configuration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0) Hold Time
BREQ0#, FLUSH#, INIT#, PICD0) Hold Time
2 20 BCLKs 11
After clock that
deasserts RESET#
deasserts RESET#
T18
RESET#/PWRGOOD Setup Time
1
ms
12
Before deassertion of
RESET#
RESET#
1
T18A
VCCT to VTTPWRGD Setup Time
1
ms
12
T18B
VCC to PWRGOOD Setup Time
10
ms
12
T18C
BSEL, VID valid time before VTTPWRGD
assertion
assertion
1
µs
12
T18D
RESET# inactive to Valid Outputs
1
BCLK 11
T18E
RESET# inactive to Drive Signals
4
BCLKs 11
T19A
Time from VCC(nominal)-12% to PWRGOOD
low
low
0
ns
13
VCC(nominal) is the VID
voltage setting
voltage setting
T19B
All outputs valid after PWRGOOD low
0
ns
13
T19C
All inputs required valid after PWRGOOD low 0
ns
13
T20A
Time from VCCT-12% to VTTPWRGD low
0
ns
14
T20B
All outputs valid after VTTPWRGD low
0
ns
14
T20C
All inputs required valid after VTTPWRGD low 0
ns
14
T20D
VID, BSEL signals valid after VTTPWRGD
low
low
0 ns 14
T20E
VTTPWRGD Transition Time
100
µs
Measurement from 300
mV to 900 mV. Amount of
noise (glitch) less than
100 mV. See Section
4.3.1 for details
mV to 900 mV. Amount of
noise (glitch) less than
100 mV. See Section
4.3.1 for details
NOTE: At least 1 ms must pass after PWRGOOD rises above V
IH18min
and BCLK, BCLK# meet their AC timing
specification until RESET# may be deasserted.