Intel E3-1105C AV8062701048800 Hoja De Datos
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AV8062701048800
Interfaces
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012
Datasheet - Volume 1 of 2
Document Number: 327405
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001
29
3.1.5.1
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
3.1.5.2
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
3.1.5.3
Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
3.1.5.4
Memory Type Range Registers (MTRRs) Enhancement
In this processor there are additional 2 MTRRs (total 10 MTRRs). These additional
MTRRs are specially important in supporting larger system memory beyond 4GB.
3.1.6
Data Scrambling
The memory controller incorporates a DDR3 Data Scrambling feature to minimize the
impact of excessive di/dt on the platform DDR3 VRs due to successive 1's and 0's on
the data bus. Past experience has demonstrated that traffic on the data bus is not
random and can have energy concentrated at specific spectral harmonics creating high
di/dt which is generally limited by data patterns that excite resonance between the
package inductance and on die capacitances. As a result the memory controller uses a
data scrambling feature to create pseudo-random patterns on the DDR3 data bus to
reduce the impact of any excessive di/dt.
3.1.7
DRAM Clock Generation
Every supported DIMM has two differential clock pairs. There are total of four clock
pairs driven directly by the processor to two DIMMs.
3.2
PCI Express* Interface
This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express*.
The processor has a total of 20 PCI Express* lanes. These lanes are fully compliant with
PCI Express Base Specification Revision 2.0. This section will discuss how these 20 PCI
Express* lanes can be utilized in various configurations on the platform.