Intel E3-1105C AV8062701048800 Hoja De Datos
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AV8062701048800
Interfaces
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012
Datasheet - Volume 1 of 2
Document Number: 327405
-
001
35
3.2.5
Configuring PCIe* Lanes
Note:
The controllers in Port 1 cannot be used to function with the controller in Port 2.
Therefore, the x16 lanes of Port 1 must not be combined with the x4 lanes of Port 2.
The following details apply to the 3 controllers in Port 1, as Port 2 cannot be bifurcated.
The configuration of the PCIe* bus is statically determined by the pre-boot software
prior to initialization. The pre-boot software determines the configuration by looking at
the two configuration pins, CFG[6:5], that determine whether the additional 2
controllers of the 16 lanes need to be enabled or not. These strap values are read upon
power up and the pre-boot software enables the appropriate number of controllers in
use as follows:
No strapping is required to enable the additional four lanes (lanes [16-19]) in any of
the permissible modes as it has a single dedicated controller.
the permissible modes as it has a single dedicated controller.
The CFG[6:5] inputs have a default value of [1:1] if they are not terminated on the
board. By default, a single x16 controller is enabled. When a logic 0 is required on the
strap, it is recommended that they be pulled down to ground with a 1 K Ohm resistor
Note:
If the x16 controller is enabled by the hardware strapping and a x8 device is plugged
in, the controller automatically operates in the x8 mode. The same is true for any
controller that is connected to a device operating at narrower lane widths.
Hot plug is not supported on these PCIe* interfaces. If a device is not present at power
up, it is not detected when it is plugged in after power up. Also, the strap values are
read upon power up and the pre-boot software enables the appropriate controller
based on the value read on CFG[6:5]. Hence, if a device of lower lane width than the
width of the controller that is enabled is plugged in before power up, then it is
automatically detected. But if a device with higher lane width is plugged in, the device
is not detected. The same is true for the number of controllers enabled. If a single
controller is enabled at power up, then a single device of any width equal to or lower
than the width of the controller is detected.
For example, if upon power up, the value on CFG [6:5] is [1:1], then the 1x16
controller is enabled. A single device of width x16 will be detected upon power up. But
if two devices of any lower width are plugged in; only the device connected to Device 1,
Function 0 will be detected.
Table 3-5.
Hardware Straps for PCIe* Controller Enabling (Port 1 Only)
CFG [6:5]
Mode
00
1x8 +2x4
01
Reserved
10
2x8
11 (default)
1x16