Intel S1400SP4 BBS1400SP4 Manual De Usuario
Los códigos de productos
BBS1400SP4
Functional Architecture
Intel® Server Board S1400SP TPS
Revision 1.0
Intel order number G64248-001
20
The following are generic DIMM population requirements that generally apply to the Intel
®
Server Board S1400SP.
All DIMMs must be DDR3 DIMMs.
• Registered DIMMs must be ECC only; unbuffered DIMMs can be ECC or non-ECC.
However, Intel
®
only validates and supports ECC memory for its server products.
Mixing of Registered and Unbuffered DIMMs is not allowed per platform.
Mixing of DDR3 voltages is not validated within a socket or across sockets by Intel
®
. If
1.35V (DDR3L) and 1.50V (DDR3) DIMMs are mixed, the DIMMs will run at 1.50V.
Mixing of DDR3 operating frequencies is not validated within a socket or across sockets
by Intel
by Intel
®
. If DIMMs with different frequencies are mixed, all DIMMs will run at the
common lowest frequency.
Quad rank DIMMs are NOT supported.
LR (Load Reduced) DIMMs are NOT supported.
A maximum of four logical ranks (ranks seen by the host) per channel is allowed.
Mixing of ECC and non-ECC DIMMs is not allowed per platform.
DIMMs with different timing parameters can be installed on different slots within the
same channel, but only timings that support the slowest DIMM will be applied to all. As a
consequence, faster DIMMs will be operated at timings supported by the slowest DIMM
populated.
same channel, but only timings that support the slowest DIMM will be applied to all. As a
consequence, faster DIMMs will be operated at timings supported by the slowest DIMM
populated.
When one DIMM is used, it must be populated in the BLUE DIMM slot (farthest away
from the CPU) of a given channel.
from the CPU) of a given channel.
When single and dual rank DIMMs are populated for 2DPC, always populate the higher
number rank DIMM first (starting from the farthest slot), for example, first dual rank, and
then single rank DIMM.
number rank DIMM first (starting from the farthest slot), for example, first dual rank, and
then single rank DIMM.
DIMM population rules require that DIMMs within a channel be populated starting with the BLUE
DIMM slot or DIMM farthest from the processor in a “fill-farthest” approach. Intel
®
MRC will
check for correct DIMM placement.
3.2.2.3
Publishing System Memory
The BIOS displays the “Total Memory” of the system during POST if Display Logo is
disabled in the BIOS setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the
system.
disabled in the BIOS setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the
system.
The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term
Effective Memory refers to the total size of all DDR3 DIMMs that are active (not
disabled) and not used as redundant units.
Effective Memory refers to the total size of all DDR3 DIMMs that are active (not
disabled) and not used as redundant units.
The BIOS provides the total memory of the system in the main page of the BIOS setup.
This total is the same as the amount described by the first bullet above.
This total is the same as the amount described by the first bullet above.
If Display Logo is disabled, the BIOS displays the total system memory on the diagnostic
screen at the end of POST. This total is the same as the amount described by the first
bullet above.
screen at the end of POST. This total is the same as the amount described by the first
bullet above.