Intel Core 2 Extreme QX9300 BX80562QX9300 Manual De Usuario
Los códigos de productos
BX80562QX9300
Datasheet
65
Package Mechanical Specifications and Pin Information
TEST1,
TEST2,
TEST3,
TEST4,
TEST5,
TEST6
TEST7
TEST2,
TEST3,
TEST4,
TEST5,
TEST6
TEST7
Input
Refer to the appropriate platform design guide for further TEST1,
TEST2, TEST3, TEST4, TEST5, TEST6 and TEST7 termination
requirements and implementation details.
TEST2, TEST3, TEST4, TEST5, TEST6 and TEST7 termination
requirements and implementation details.
THERMTRIP#
Output
The processor protects itself from catastrophic overheating by use
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
THRMDA
Other
Thermal Diode Anode.
THRMDA_2
Other
Thermal Diode Anode of the second die.
THRMDC
Other
Thermal Diode Cathode.
THRMDC_2
Other
Thermal Diode Cathode of the second die.
TMS
Input
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
by debug tools.
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that it
is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of both FSB agents.
is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of both FSB agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
VCC
Input
Processor core power supply.
VCCA
Input
VCCA provides isolated power for the internal processor core PLLs
.
VCCP
Input
Processor I/O Power Supply.
VCCSENSE
Output
VCCSENSE together with VSSSENSE are voltage feedback signals
that control the 2.1 mΩ loadline at the processor die. It should be
used to sense voltage near the silicon with little noise.
that control the 2.1 mΩ loadline at the processor die. It should be
used to sense voltage near the silicon with little noise.
VID[6:0]
Output
VID[6:0] (Voltage ID) pins are used to support automatic selection
of power supply voltages (V
of power supply voltages (V
CC
). Unlike some previous generations
of processors, these are CMOS signals that are driven by the
processor. The voltage supply for these pins must be valid before
the VR can supply V
processor. The voltage supply for these pins must be valid before
the VR can supply V
CC
to the processor. Conversely, the VR output
must be disabled until the voltage supply for the VID pins becomes
valid. The VID pins are needed to support the processor voltage
specification variations. See
valid. The VID pins are needed to support the processor voltage
specification variations. See
for definitions of these pins.
The VR must supply the voltage that is requested by the pins, or
disable itself.
disable itself.
VSS
Input
Processor core ground node.
VSSSENSE
Output
VSSSENSE
together with VCCSENSE
are voltage feedback signals
that control the 2.1-mΩ loadline at the processor die. It should be
used to sense ground near the silicon with little noise.
used to sense ground near the silicon with little noise.
Table 14.
Signal Description (Sheet 9 of 9)
Name
Type
Description