Intel C2338 FH8065501516761 Hoja De Datos
Los códigos de productos
FH8065501516761
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
239
Volume 2—PCI Express Root Ports (RP)—C2000 Product Family
PCI Express RAS Features
12.9
PCI Express RAS Features
The PCI Express Base Specification, Revision 2.1 defines a standard set of error
reporting mechanisms. The root ports supports all of them including Error Poisoning
and Advanced Error Reporting (AER).
The root ports also support:
• Link-Level Cyclical Redundancy Code (LCRC) and Retry Management as described
in Section 3.5. Data Integrity, of the specification.
• Dynamic Link Width (DLW) reduction on link failure. See Section 4.2.4. Link
Initialization and Training, of the specification.
12.9.1
Error Detecting, Reporting and Logging
The PCI Express Root Ports provide error detection and logging as specified in the
aforementioned specification.
Error messages from the PCI Express Functions or Devices in the hierarchy associated
with the root port are detected. The root port, if enabled to do so, reports an interrupt
to the CPU. The three classes of errors are:
• Fatal Error (ERR_FATAL Error Message)
Uncorrectable error conditions which render the particular link and related
hardware unreliable. For fatal errors, a reset of the components on the link is
required to return to reliable operation.
• Non-Fatal Error (ERR_NONFATAL Error Message)
Uncorrectable errors which cause a particular transaction to be unreliable but
the link is otherwise fully functional. Isolating non-fatal from fatal errors
provides requester/receiver logic in a device or system management software
the opportunity to recover from the error without resetting the components on
the link and disturbing other transactions in progress. Devices not associated
with the transaction in error are not impacted by the error.
• Correctable Error (ERR_COR Error Message)
Correctable errors include those error conditions where the hardware recovers
without any loss of information. The hardware corrects these errors and
software intervention is not required.
Each error class generates an interrupt to the CPU if the corresponding error class
Reporting Enable is set in the Root Port Root Error Command register. This register is
located in the configuration space of the root port in its PCI Express Advanced Error
Reporting (AER) Extended Capability Structure.
The root port itself as a PCI Express Device also generates the three classes of error
messages to the root complex if the particular error class is enabled in the Root Port
Device Command register in its PCI Express Capability Registers in Configuration
Space.
Another way to enable error reporting by the root port is the Root Port PCI Command
register contains SERR# Enable (SEE). When set, this bit enables reporting of non-fatal
and fatal errors detected by root port to the root complex. This bit also controls
transmission by the root port of ERR_NONFATAL and ERR_FATAL error messages
forwarded from the downstream interface. ERR_COR messages are not affected by this
bit.
Devices and Functions in the downstream hierarchy that support the AER Capability,
and the root ports themselves as devices, also have an Uncorrectable Error Mask
register and a Correctable Error Mask register allows each error condition to be masked
independently.