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FH8065401488912

Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family

Power Up from G3 State (Mechanical Off)

Intel

Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

126

Order Number: 330061-002US

7.1.3

SUS Power Well Power-Up Sequence From the G3 State

Refer to

, and

Some of the pin-based straps (hard straps) values are sampled by the SoC when the

active-low RSMRST_B signal is deasserted. These “SUS Power OK” hard strap values

must be valid for at least 400 ns after RSMRST_B signal is deasserted. Hard straps are

. Important to the

SoC power-up sequence is the sampling of the SoC pin Y65 which is the “After G3

Enable” (AG3E) hard strap. Its effect is mentioned later.

Figure 7-1. Power-Up SUS Power Well Voltages to S5 State (with RTC Battery)

VRTC3P0 Voltage Valid

SoC input:

RTEST_B

SoC input:

SRTCRST_B

Undefined

All Standby Voltages Valid

and GbE Reference Clock

stable at SoC input pins

Undefined

SoC input:

RSMRST_B

Undefined

SoC input:

COREPWROK

Undefined

SoC output:

PMU_SLP_S45_B

Undefined

SoC output:

SUSPWRDNACK

Undefined