Intel C2550 FH8065401488912 Hoja De Datos
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FH8065401488912
Volume 2—PCI Express Root Ports (RP)—C2000 Product Family
Power Management
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
232
Order Number: 330061-002US
12.5.1
Hot-Plug Events
The
SoC
PCI Express* Root Ports do not support the hot-add and hot-removal of PCI
Express adapters. The PCIe* specification calls this PCI Express Hot-Plug* support. The
root ports also do not support the detection of an adapter that has been newly
plugged-in (connected) or newly powered-on.
12.5.2
System Error (SERR)
System Error events are supported by both internal and external sources and are
mapped to generate either a Non-Maskable Interrupt (NMI) or a System Management
Interrupt (SMI). See the PCI Express Base Specification, Revision 2.1 for details.
12.6
Power Management
Each root port link supports L0 and L1 link states per PCI Bus Power Management
Interface Specification, Revision 1.2.
12.7
Physical Layer
12.7.1
PCI Express Speed Support
The PCI Express (PCIe) physical layer implements high-speed, low-voltage differential
signaling that is described in detail in the PCI Express Base Specification, Revision 2.1.
The integrated root ports support 2.5 GT/s and 5 GT/s PCI Express speeds. The Root
Port controllers negotiate the speed using the in-band signaling mechanism defined in
Section 4.2.4, Link Initialization and Training, of the specification.
The PCI Express Root Ports use 8b/10b encoding when the data rate is 2.5 GT/s or 5
GT/s.
12.7.2
Form Factor Support
The PCIe controllers support card-edge-connector and Server I/O Module (SIOM) form-
factors. Form-factor-specific differences that exist for Hot-Plug and power management
are captured in their individual sections elsewhere in this chapter.
The root ports have enough buffering to provide full performance using up to a 20-inch
trace of FR4 with two connectors. They do not provide any additional buffering for
cable/repeater latencies and are not able to achieve full bandwidth on PCI Express
using these topologies. But functionally, they are able to support cables. Refer to the
Edisonville/Rangeley Platform Design Guide (PDG) for interface topologies supported.