Intel E3845 FH8065301487715 Hoja De Datos
Los códigos de productos
FH8065301487715
SIO - I
2
C Interface
Intel
®
Atom™ Processor E3800 Product Family
3822
Datasheet
26.2.3.1
START and STOP Conditions
When the bus is idle, both the clock and data signals are pulled high through external
pull-up resistors on the bus.
pull-up resistors on the bus.
When the master wants to start a transmission on the bus, the master issues a START
condition.
condition.
•
This is defined to be a high-to-low transition of the data signal while the clock is
high.
high.
•
When the master wants to terminate the transmission, the master issues a STOP
condition. This is defined to be a low-to-high transition of the data line while the
clock is high.
condition. This is defined to be a low-to-high transition of the data line while the
clock is high.
shows the timing of the START and STOP conditions.
•
When data is being transmitted on the bus, the data line must be stable when the
clock is high.
clock is high.
The signal transitions for the START/STOP conditions, as depicted above, reflect those
observed at the output of the master driving the I
observed at the output of the master driving the I
2
C bus. Care should be taken when
observing the data/clock signals at the input of the slave(s), because unequal line
delays may result in an incorrect data/clock timing relationship.
delays may result in an incorrect data/clock timing relationship.
26.2.3.2
Addressing Slave Protocol
There are two address formats—seven-bit address format and 10-bit address format.
Seven-bit Address Format
•
During the seven-bit address format, the first seven bits (bits 7:1) of the first byte
set the slave address and the LSB bit (bit 0) is the R/W bit as shown in
set the slave address and the LSB bit (bit 0) is the R/W bit as shown in
.
•
When bit 0 (R/W) is set to 0, the master writes to the slave. When bit 0 (R/W) is
set to 1, the master reads from the slave.
set to 1, the master reads from the slave.
Figure 121.START and STOP Conditions
Data
Clock
Start Conditions
Change of Data Allowed
Data Line Stable
Data Line Valid
Stop Condition
Change of Data Allowed
S
P