Intel E3845 FH8065301487715 Hoja De Datos
Los códigos de productos
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4599
39.7.23
South Core Trigger Negative Enable 4
(cfio_ioreg_SC_TNE_127_96_)—Offset 70h
Access via PCU proxy, the register trigger Negative Edge Enable: When set to a 1, the
corresponding GPIO signal (if enabled in the GPIO_USE_SEL register) will case an GPE
or SMI when a 1 to 0 transition occurs. When set to 0, the GPIO signal is not enabled to
trigger an GPE or SMI on a 1 to 0 transition. - Only the 8 lsb are used in VLV
Access Method
Default: 00000000h
39.7.24
South Core Trigger Status 4 (cfio_ioreg_SC_TS_127_96_)—
Offset 74h
When set to a 1, the corresponding GPIO (if enabled in the GPIO_USE_SEL register) if
enabled as input via IO_SEL(n), triggered an GPE or SMI. This will be set if a 0 to 1
transition occurred and TPE(n) was set, or a 1 to 0 transition occurred and TNE(n) was
set. If both TPE(n) and TNE(n) are set, then this bit will be set on both a 0 to 1 and a 1
to 0 transition. This bit will not be set if the GPIO is configured as an output. - Only the
8 lsb are used in VLV
Access Method
5:0
0b
RW
Tpe (tpe):
bit 5 - PLT_CLK5
bit 4 - PLT_CLK4
bit 3 - PLT_CLK3
bit 2 - PLT_CLK2
bit 1 - PLT_CLK1
bit 0 - PLT_CLK0
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
I/O Register
(Size: 32 bits)
Offset:
GBASE Type:
PCI Configuration Register (Size: 32 bits)
GBASE Reference:
[B:0, D:31, F:0] + 48h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
res
er
ved
tne
Bit
Range
Default &
Access
Field Name (ID): Description
31:6
000000000
000000000
00000000b
RO
Reserved (reserved):
reserved
5:0
0b
RW
Tne (tne):
bit 5 - PLT_CLK5
bit 4 - PLT_CLK4
bit 3 - PLT_CLK3
bit 2 - PLT_CLK2
bit 1 - PLT_CLK1
bit 0 - PLT_CLK0