Intel E3815 FH8065301567411 Hoja De Datos

Intel

®

 Atom™ Processor E3800 Product Family

4422

Datasheet

This register is a combination of two registers: the interrupt identification register (IIR) 

that is a read-only register and the FIFO control register (FCR) that is a write-only 

register. If FIFOs are not implemented, the FIFO control register does not exist and 

writing to this register address has no effect.

Default: 01h

7:0

00h

RW

, This field is used as interrupt enable 

register. The smartest way to perform serial communications on a PC is using interrupt 

driven routines. In that configuration, it is not necessary to poll the registers of the 

UART periodically for state changes. The UART will signal each change by generating a 

processor interrupt. A software routine must be present to handle the interrupt and to 

check what state change was responsible for it. Interrupts are not generated, unless the 

UART is told to do so. This is done by setting bits in the IER, interrupt enable register. A 

bit value 1 indicates, that an interrupt may take place. Bit  Description  0   ERBFI - 

Enable Received Data Available Interrupt. This is used to enable/disable the generation 

of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO 

mode and FIFOs enabled). These are the second highest priority interrupts.  1   ETBEI - 

Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the 

generation of Transmitter Holding Register Empty Interrupt. This is the third highest 

priority interrupt.  2   ELSI - Enable Receiver Line Status Interrupt. This is used to 

enable/disable the generation of Receiver Line Status Interrupt. This is the highest 

priority interrupt.  3   EDSSI - Enable Modem Status Interrupt. This is used to enable/

disable the generation of Modem Status Interrupt. This is the fourth highest priority 

interrupt.  4   Reserved and read as zero  5   Reserved and read as zero  6   Reserved 

and read as zero  7   PTIME - Programmable THRE Interrupt Mode Enable that can be 

written to only when THRE_MODE_USER == Enabled, always readable. This is used to 

enable/disable the generation of THRE Interrupt. If DLAB=1'b1, this register is used as 

DLM (Divisor Latch MSB). See DLL field description in the Rx_Tx_Buffer register.

I/O Register

(Size: 8 bits)

7

4

0

0

0

0

0

0

0

0

1

FER

T

TE

T

IIR

7:6

00b

RO

 from this field is used to indicate 

whether the FIFOs are enabled or disabled. '00' - disabled '11' - enabled Write to this 

field is used to select the trigger level in the receiver FIFO at which the Received Data 

Available Interrupt is generated. In auto flow control mode it is used to determine when 

the rts_n signal is de-asserted. The following trigger levels are supported: '00' - 1 

character in the FIFO '01' - FIFO 1/4 full '10' - FIFO 1/2 full '11' - FIFO 2 less than full

5:4

00b

RO

 from this field is reserved and should return zero 

 to this field is used to select the empty threshold level at which the THRE 

Interrupts are generated when the mode is active. The following trigger levels are 

supported: '00' - FIFO empty '01' - 2 characters in the FIFO '10' - FIFO 1/4 full '11' - 

FIFO 1/2 full