Intel N2820 FH8065301616603 Hoja De Datos
Los códigos de productos
FH8065301616603
Datasheet
711
Low Power Engine (LPE) for Audio (I
2
S)
For the PSP format, the Idle and Disable modes of the I2Sx_DATAOUT, I2Sx_CLK, and
I2Sx_FRM are programmable by means of the SSPSP.ETDS, SSPSP.SCMODE and
SSPSP.SFRMP bits. When Transmit data is ready, the I2Sx_CLK will remain in its Idle
state for the number of serial clock (I2Sx_CLK) clock periods programmed within the
Start Delay (SSPSP.STRTDLY) field. I2Sx_CLK will then start toggling, I2Sx_DATAOUT
will remain in the idle state for the number of cycles programmed within the Dummy
Start (SSPSP.DMYSTRT) field. The I2Sx_FRM signal will be asserted after the number of
half-clocks programmed in the SSPSP.SFRDLY field. The I2Sx_FRM signal will remain
asserted for the number of clocks programmed within the SSPSP.SFRMWDTH then de-
assert. Four to 32 bits can be transferred per frame. Once the last bit (LSB) is
transferred, the I2Sx_CLK will continue toggling based off the Dummy Stop
(SSPSP.DMYSTOP) field. I2Sx_DATAOUT either retains the last value transmitted or is
forced to zero, depending on the value programmed within the End of Transfer Data
State (SSPSP.ETDS) field, when the controller goes into Idle mode, unless the
Enhanced SSP port is disabled or reset (which forces I2Sx_DATAOUT to zero).
I2Sx_FRM are programmable by means of the SSPSP.ETDS, SSPSP.SCMODE and
SSPSP.SFRMP bits. When Transmit data is ready, the I2Sx_CLK will remain in its Idle
state for the number of serial clock (I2Sx_CLK) clock periods programmed within the
Start Delay (SSPSP.STRTDLY) field. I2Sx_CLK will then start toggling, I2Sx_DATAOUT
will remain in the idle state for the number of cycles programmed within the Dummy
Start (SSPSP.DMYSTRT) field. The I2Sx_FRM signal will be asserted after the number of
half-clocks programmed in the SSPSP.SFRDLY field. The I2Sx_FRM signal will remain
asserted for the number of clocks programmed within the SSPSP.SFRMWDTH then de-
assert. Four to 32 bits can be transferred per frame. Once the last bit (LSB) is
transferred, the I2Sx_CLK will continue toggling based off the Dummy Stop
(SSPSP.DMYSTOP) field. I2Sx_DATAOUT either retains the last value transmitted or is
forced to zero, depending on the value programmed within the End of Transfer Data
State (SSPSP.ETDS) field, when the controller goes into Idle mode, unless the
Enhanced SSP port is disabled or reset (which forces I2Sx_DATAOUT to zero).
With the assertion of I2Sx_FRM, Receive data is simultaneously driven from the
peripheral on I2Sx_DATAIN, most significant bit first. Data transitions on I2Sx_CLK
based on the Serial Clock Mode selected and is sampled by the controller on the
opposite edge. When the Enhanced SSP is a master to the frame synch (I2Sx_FRM)
and a slave to the clock (I2Sx_CLK), then at least three extra clocks (I2Sx_CLKs) will
be needed at the beginning and end of each block of transfers to synchronize control
signals from the APB clock domain into the SSP clock domain (a block of transfers is a
group of back-to-back continuous transfers).
peripheral on I2Sx_DATAIN, most significant bit first. Data transitions on I2Sx_CLK
based on the Serial Clock Mode selected and is sampled by the controller on the
opposite edge. When the Enhanced SSP is a master to the frame synch (I2Sx_FRM)
and a slave to the clock (I2Sx_CLK), then at least three extra clocks (I2Sx_CLKs) will
be needed at the beginning and end of each block of transfers to synchronize control
signals from the APB clock domain into the SSP clock domain (a block of transfers is a
group of back-to-back continuous transfers).
Figure 24. Programmable Serial Protocol Format
NOTE: When in PSP format, if the SSP is the master of the clock (I2Sx_CLK is an output) and the SSPSP.ETDS bit
is cleared, the End of Transfer Data State for the I2Sx_DATAOUT line is 0. If the SSP is the master of the
clock, and the SSPSP.ETDS bit is set, the I2Sx_DATAOUT line remains at the last bit transmitted (LSB). If
the SSP is a slave to the clock (I2Sx_CLK is an input), and modes 1 or 3 are used, the ETDS can only
change from the LSB if more clocks (I2Sx_CLK) are sent to the SSP (that is, dummy stop clocks or slave
clock is free running.
clock, and the SSPSP.ETDS bit is set, the I2Sx_DATAOUT line remains at the last bit transmitted (LSB). If
the SSP is a slave to the clock (I2Sx_CLK is an input), and modes 1 or 3 are used, the ETDS can only
change from the LSB if more clocks (I2Sx_CLK) are sent to the SSP (that is, dummy stop clocks or slave
clock is free running.
LSB
End of Transfer
Data State
MSB
LSB
MSB
T1
T2
T5
T6
T3
T4
SSPSP.SCMODE
I2Sx_CLK
00
01
10
11
I2Sx_DATAOUT
I2Sx_DATAOUT
SSPSP.SFRMP=1
SSPSP.SFRMP=0
I2Sx_FRM