Intel N2820 FH8065301616603 Hoja De Datos
Los códigos de productos
FH8065301616603
Low Power Engine (LPE) for Audio (I
2
S)
714
Datasheet
above the most significant bit (that is, DMA and CPU access do not have to write to the
unused bit locations). Logic in the Enhanced SSP automatically formats data in the
Transmit FIFO so that the sample is properly transmitted on I2Sx_DATAOUT in the
selected frame format.
unused bit locations). Logic in the Enhanced SSP automatically formats data in the
Transmit FIFO so that the sample is properly transmitted on I2Sx_DATAOUT in the
selected frame format.
Two separate and independent FIFOs are present for Transmit (to peripheral) and
Receive (from peripheral) serial data. FIFOs are filled or emptied by programmed I/O or
DMA bursts.
Receive (from peripheral) serial data. FIFOs are filled or emptied by programmed I/O or
DMA bursts.
16.7.1.1
Programmed IO Considerations
FIFO filling and emptying can be performed by the processor in response to an
Interrupt from the FIFO logic. Each FIFO has a programmable FIFO trigger threshold at
which an Interrupt is triggered. When the number of entries in the Receive FIFO
exceeds the SSCR1.RFT value, an interrupt is generated (if enabled), which signals the
CPU to empty the Receive FIFO. When the number of entries in the Transmit FIFO is
less than or equal to the SSCR1.TFT value plus 1, an Interrupt is generated (if
enabled), which signals the CPU to refill the Transmit FIFO.
Interrupt from the FIFO logic. Each FIFO has a programmable FIFO trigger threshold at
which an Interrupt is triggered. When the number of entries in the Receive FIFO
exceeds the SSCR1.RFT value, an interrupt is generated (if enabled), which signals the
CPU to empty the Receive FIFO. When the number of entries in the Transmit FIFO is
less than or equal to the SSCR1.TFT value plus 1, an Interrupt is generated (if
enabled), which signals the CPU to refill the Transmit FIFO.
Users can also poll the Enhanced SSP Status register to determine how many samples
are in a FIFO, and whether the FIFO is full or empty. Software is responsible for
ensuring that the proper RFT and TFT values are chosen to prevent ROR and TUR error
conditions.
are in a FIFO, and whether the FIFO is full or empty. Software is responsible for
ensuring that the proper RFT and TFT values are chosen to prevent ROR and TUR error
conditions.
Note:
If the software attempts to read from an empty Receive FIFO, it will receive a duplicate
of the previously read value.
of the previously read value.
16.7.1.2
DMA Considerations
The DMA controller can also be programmed to transfer data to and from the Enhanced
SSP FIFOs. To prevent over-runs of the Transmit FIFO or under-runs of the Receive
FIFO when using the DMA, be careful when setting the Transmit and Receive FIFO
trigger threshold levels.
SSP FIFOs. To prevent over-runs of the Transmit FIFO or under-runs of the Receive
FIFO when using the DMA, be careful when setting the Transmit and Receive FIFO
trigger threshold levels.
There are restrictions on how the DMA can be programmed when used with the SSP
Controller.
Controller.
•
The DMA Transfer Width must be greater than or equal to the SSP data size. For
example if the SSP Data Size is 16b then the DMA Transfer Width should be 16b.
example if the SSP Data Size is 16b then the DMA Transfer Width should be 16b.
•
The DMA may not support the DMA Transfer Width of the SSP Data Size and
therefore the DMA Transfer Width must be larger than the SSP Data Size. If this is
the case then software must manage any extra data bits.
therefore the DMA Transfer Width must be larger than the SSP Data Size. If this is
the case then software must manage any extra data bits.
•
The DMA Burst Transaction Length for RX must be less than or equal to the RX
Threshold.
Threshold.
•
The DMA Burst Transaction Length for TX must be less than or equal to the number
of empty locations in the TX FIFO. A safe value is the Total TX FIFO Size - TX
Threshold.
of empty locations in the TX FIFO. A safe value is the Total TX FIFO Size - TX
Threshold.
•
DMA must be in Fixed Address mode to read or write the SSP Data Register.