Texas TMS320C645X Manual De Usuario
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5.26
DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR)
SRIO Registers
Each of the four doorbells is supported by a register of this type.
Figure 82. DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR)
31
28
27
24
23
20
19
16
ICR7
ICR6
ICR5
ICR4
R/W-0x00
R/W-0x00
R/W-0x00
R/W-0x00
15
12
11
8
7
4
3
0
ICR3
ICR2
ICR1
ICR0
R/W-0x00
R/W-0x00
R/W-0x00
R/W-0x00
LEGEND: R = Read, W = Write, n = value at reset
Table 56. DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) Field
Descriptions
Bit
Field
Value
Description
31-0
ICR (0-7)
Doorbell n (0 to 3) CPU servicing interrupt condition routing bits
SPRU976 – March 2006
Serial RapidIO (SRIO)
127