Renesas Stereo System SH7709S Manual De Usuario

Rev. 5.00, 09/03, page 140 of 760

IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have
been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.

Bit:

7

6

5

4

3

2

1

0

TXI1R

BRI1R

RXI1R

ERI1R

DEI3R

DEI2R

DEI1R

DEI0R

Initial  value:

0

0

0

0

0

0

0

0

R/W:

R

R

R

R

R

R

R

R

Bit 7—TXI1 Interrupt Request (TXI1R): Indicates whether a TXI1 (IrDA) interrupt request has
been generated.

0

TXI1 interrupt request not generated

(Initial value)

1

TXI1 interrupt request generated

Bit 6—BRI1 Interrupt Request (BRI1R): Indicates whether a BRI1 (IrDA) interrupt request has
been generated.

0

BRI1 interrupt request not generated

(Initial value)

1

BRI1 interrupt request generated

Bit 5—RXI1 Interrupt Request (RXI1R): Indicates whether an RXI1 (IrDA) interrupt request
has been generated.

0

RXI1 interrupt request not generated

(Initial value)

1

RXI1 interrupt request generated

Bit 4—ERI1 Interrupt Request (ERI1R): Indicates whether an ERI1 (IrDA) interrupt request
has been generated.

0

ERI1 interrupt request not generated

(Initial value)

1

ERI1 interrupt request generated