Renesas Stereo System SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 206 of 760
9.2.2
CPG Pin Configuration
Table 9.1 lists the CPG pins and their functions.
Table 9.1
CPG Pins and Functions
Pin Name
Symbol
I/O
Description
MD0
I
Set the clock operating mode
MD1
I
Mode control
pins
pins
MD2
I
XTAL
O
Connects a crystal oscillator
Crystal I/O pins
(clock input pins)
(clock input pins)
EXTAL
I
Connects a crystal oscillator. Also used to input an
external clock
external clock
Clock I/O pin
CKIO
I/O
Inputs or outputs an external clock
CAP1
I
Connects capacitor for PLL circuit 1 operation
(recommended value 470 pF)
(recommended value 470 pF)
Capacitor
connection pins
for PLL
connection pins
for PLL
CAP2
I
Connects capacitor for PLL circuit 2 operation
(recommended value 470 pF)
(recommended value 470 pF)
9.2.3
CPG Register Configuration
Table 9.2 shows the CPG register configuration.
Table 9.2
CPG Register
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Frequency control register
FRQCR
R/W
H'0102
H'FFFFFF80
16