Renesas Stereo System SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 260 of 760
10.3
BSC Operation
10.3.1
Endian/Access Size and Data Alignment
The SH7709S supports both big endian, in which the 0 address is the most significant byte in the
byte data, and little endian, in which the 0 address is the least significant byte. Switching between
the two is designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-
on reset, big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
byte data, and little endian, in which the 0 address is the least significant byte. Switching between
the two is designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-
on reset, big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus
widths (word and longword) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word. This means data alignment is done by matching the device’s data width and
endian. The access unit must also be matched to the device’s bus width. This also means that when
longword data is read from a byte-width device, four read operations must be performed. In the
SH7709S, data alignment and conversion of data length is performed automatically between the
respective interfaces.
widths (word and longword) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word. This means data alignment is done by matching the device’s data width and
endian. The access unit must also be matched to the device’s bus width. This also means that when
longword data is read from a byte-width device, four read operations must be performed. In the
SH7709S, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 10.7 to 10.12 show the relationship between endian, device data width, and access unit.
Table 10.7
32-Bit External Device/Big-Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31–D24
D23–D16
D15–D8
D7–D0
W
W
W
WE
EE
E3333
,
DQMUU
W
W
W
WE
EE
E2222
,
DQMUL
W
W
W
WE
EE
E1111
,
DQMLU
W
W
W
WE
EE
E0000
,
DQMLL
Byte access
at 0
at 0
Data
7–0
7–0
—
—
—
Asserted
Byte access
at 1
at 1
—
Data
7–0
7–0
—
—
Asserted
Byte access
at 2
at 2
—
—
Data
7–0
7–0
—
Asserted
Byte access
at 3
at 3
—
—
—
Data
7–0
7–0
Asserted
Word access
at 0
at 0
Data
15–8
15–8
Data
7–0
7–0
—
—
Asserted
Asserted
Word access
at 2
at 2
—
—
Data
15–8
15–8
Data
7–0
7–0
Asserted
Asserted
Longword
access at 0
access at 0
Data
31–24
31–24
Data
23–16
23–16
Data
15–8
15–8
Data
7–0
7–0
Asserted
Asserted
Asserted
Asserted