Renesas Stereo System SH7709S Manual De Usuario

Rev. 5.00, 09/03, page 376 of 760

The DMAC has an on-chip compare match timer (CMT) to generate DMA transfer requests. The
CMT has a 16-bit counter.

The CMT has the following features:

•

 

Four types of counter input clock can be selected



 

One of four internal clocks (P

φ

/4, P

φ

/8, P

φ

/16, P

φ

/64) can be selected.

•

 

Generates a DMA transfer request when compare match occurs.

Figure 11.24 shows a block diagram of the CMT.

Internal bus

Bus

interface

Control circuit

Clock selection

CMSTR

CMCSR0

CMCOR0

Comparator

CMCNT0

Module bus

CMT

P

φ

/4 P

φ

/8 P

φ

/16 P

φ

/64

CMSTR:

CMCSR0:

CMCOR0:

CMCNT0:

Compare match timer start register
Compare match timer control/status register 0
Compare match timer constant register 0
Compare match timer counter 0