Renesas Stereo System SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 405 of 760
12.4.2
Status Flag Clearing Timing
The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing.
P
φ
Peripheral address bus
UNF, ICPF
TCR address
T
1
T
2
TCR write cycle
T
3
Figure 12.9 Status Flag Clearing Timing
12.4.3
Interrupt Sources and Priorities
The TMU produces underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, an interrupt is requested. Codes are set in the interrupt event
registers (INTEVT, INTEVT2) for these interrupts and interrupt handling occurs according to the
codes.
interrupt enable bit are both set to 1, an interrupt is requested. Codes are set in the interrupt event
registers (INTEVT, INTEVT2) for these interrupts and interrupt handling occurs according to the
codes.
The relative priorities of channels can be changed using the interrupt controller (see section 4,
Exception Handling, and section 6, Interrupt Controller (INTC)). Table 12.3 lists TMU interrupt
sources.
Exception Handling, and section 6, Interrupt Controller (INTC)). Table 12.3 lists TMU interrupt
sources.
Table 12.3
TMU Interrupt Sources
Channel
Interrupt Source
Description
Priority
0
TUNI0
Underflow interrupt 0
High
1
TUNI1
Underflow interrupt 1
2
TUNI2
Underflow interrupt 2
2
TICPI2
Input capture interrupt 2
Low