Renesas Stereo System SH7709S Manual De Usuario

Rev. 5.00, 09/03, page 490 of 760

Figure 15.1 shows a block diagram of the smart card interface.

RxD

TxD

SCK

SCI

SCBRR

SCSCR

SCSMR

SCTDR

SCTSR

SCRDR

SCRSR

SCSCMR

SCSSR

Parity generation

Parity check

Clock

External clock

Module data bus

Internal
data bus

P

φ

P

φ

/4

P

φ

/16

P

φ

/64

TXI
RXI
ERI

Bus interface

Baud rate

generator

Transmit/

receive 

control

SCSCMR:

SCRSR:

SCRDR:

SCTSR:

SCTDR:

SCSMR:

SCSCR:

SCSSR:

SCBRR:

Legend

Smart card mode register
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register