Renesas Stereo System SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 498 of 760
In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and
communication is MSB first. The start character data is H'3F. Parity is even (from the smart
card standard), and so the parity bit is 0, which corresponds to state Z.
communication is MSB first. The start character data is H'3F. Parity is even (from the smart
card standard), and so the parity bit is 0, which corresponds to state Z.
Only data bits D7–D0 are inverted by the SINV bit. To invert the parity bit, set the O/
E bit in
SCSMR to odd parity mode. This applies to both transmission and reception.
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
A
(Z)
Z
Z
A
Z
Z
Z
A
A
Z
(Z)
State
a. Direct convention (SDIR, SINV, and O/
E are all 0)
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
A
(Z)
Z
Z
A
A
A
A
A
A
Z
(Z)
State
b. Inverse convention (SDIR, SINV, and O/
E are all 1)
Figure 15.4 Waveform of Start Character
15.3.5
Clock
Only the internal clock generated by the on-chip baud rate generator can be used as the
communication clock in the smart card interface. The bit rate for the clock is set by the bit rate
register (SCBRR) and the CKS1 and CKS0 bits in the serial mode register (SCSMR), and is
calculated using the equation below. Table 15.5 shows sample bit rates. If clock output is then
selected by setting CKE0 to 1, a clock with a frequency 372 times the bit rate is output from the
SCK0 pin.
communication clock in the smart card interface. The bit rate for the clock is set by the bit rate
register (SCBRR) and the CKS1 and CKS0 bits in the serial mode register (SCSMR), and is
calculated using the equation below. Table 15.5 shows sample bit rates. If clock output is then
selected by setting CKE0 to 1, a clock with a frequency 372 times the bit rate is output from the
SCK0 pin.
B =
×
10
6
1488
×
2
2n–1
×
(N + 1)
P
φ
Where: N
=
Value set in SCBRR (0
≤
N
≤
255)
B
=
Bit rate (bits/s)
P
φ
=
Peripheral module operating frequency (MHz)
n
=
0 to 3 (table 15.4)