Renesas Stereo System SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 511 of 760
Section 16 Serial Communication Interface with FIFO
(SCIF)
16.1
Overview
The SH7709S has a two-channel serial communication interface with FIFO (SCIF) that supports
asynchronous serial communication. It also has 16-stage FIFO registers for both transmission and
reception that enable the SH7709S to perform efficient high-speed continuous communication.
asynchronous serial communication. It also has 16-stage FIFO registers for both transmission and
reception that enable the SH7709S to perform efficient high-speed continuous communication.
16.1.1
Features
•
Asynchronous serial communication:
Serial data communication is performed by start-stop in character units. The SCI can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity and framing errors
Break detection: Break is detected when a framing error is followed by at least one frame at
the space 0 level (low level). It is also detected by reading the RxD level directly from the
port SC data register (SCPDR) when a framing error occurs.
the space 0 level (low level). It is also detected by reading the RxD level directly from the
port SC data register (SCPDR) when a framing error occurs.
•
Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
SCI can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
•
On-chip baud rate generator with selectable bit rates
•
Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
SCK pin (external)
•
Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
receive-error interrupts are requested independently. The direct memory access controller
(DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receive-
FIFO-data-full interrupt.
receive-error interrupts are requested independently. The direct memory access controller
(DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receive-
FIFO-data-full interrupt.
•
When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
power.
•
On-chip modem control functions (RTS and CTS)
•
The quantity of data in the transmit and receive FIFO registers and the number of receive
errors of the receive data in the receive FIFO register can be ascertained.
errors of the receive data in the receive FIFO register can be ascertained.
•
A time-out error (DR) can be detected when receiving.