Renesas Stereo System SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 600 of 760
19.8.2
Port G Data Register (PGDR)
Bit:
7
6
5
4
3
2
1
0
PG7DT
PG6DT
PG5DT
PG4DT
PG3DT
PG2DT
PG1DT
PG0DT
Initial value:
*
*
*
*
*
*
*
*
R/W:
R
R
R
R
R
R
R
R
Note:
*
Undefined
The port G data register (PGDR) is an 8-bit read-only register that stores data for pins PTG7 to
PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the function is general
input port, if the port is read the corresponding pin level is read. Table 19.14 shows the function of
PGDR.
PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the function is general
input port, if the port is read the corresponding pin level is read. Table 19.14 shows the function of
PGDR.
PGDR is initialized by a power-on reset, after which the general input port function (pull-up MOS
on) is set as the initial pin function, and the corresponding pin levels are read.
on) is set as the initial pin function, and the corresponding pin levels are read.
Table 19.14 Port G Data Register (PGDR) Read/Write Operations
PGnMD1
PGnMD0
Pin State
Read
Write
0
0
Other function
(see table 18.1)
(see table 18.1)
H'00
Ignored (no effect on pin state)
1
Reserved
H'00
Ignored (no effect on pin state)
1
0
Input (Pull-up
MOS on)
MOS on)
Pin state
Ignored (no effect on pin state)
1
Input (Pull-up
MOS off)
MOS off)
Pin state
Ignored (no effect on pin state)
(n = 0 to 7)