Renesas Stereo System SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 604 of 760
19.10.2
Port J Data Register (PJDR)
Bit:
7
6
5
4
3
2
1
0
PJ7DT
PJ6DT
PJ5DT
PJ4DT
PJ3DT
PJ2DT
PJ1DT
PJ0DT
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The port J data register (PJDR) is an 8-bit readable/writable register that stores data for pins PTJ7
to PTJ0. Bits PJ7DT to PJ0DT correspond to pins PTJ7 to PTJ0. When the pin function is general
output port, if the port is read the value of the corresponding PJDR bit is returned directly. When
the function is general input port, if the port is read, the corresponding pin level is read. Table
19.18 shows the function of PJDR.
to PTJ0. Bits PJ7DT to PJ0DT correspond to pins PTJ7 to PTJ0. When the pin function is general
output port, if the port is read the value of the corresponding PJDR bit is returned directly. When
the function is general input port, if the port is read, the corresponding pin level is read. Table
19.18 shows the function of PJDR.
PJDR is initialized to H'00 by a power-on reset. It retains its previous value in software standby
mode and sleep mode, and in a manual reset.
mode and sleep mode, and in a manual reset.
Table 19.18 Port J Data Register (PJDR) Read/Write Operations
PJnMD1
PJnMD0
Pin State
Read
Write
0
0
Other function
(see table 18.1)
(see table 18.1)
PJDR value
Value is written to PJDR, but does not
affect pin state
affect pin state
1
Output
PJDR value
Write value is output from pin
1
0
Input (Pull-up
MOS on)
MOS on)
Pin state
Value is written to PJDR, but does not
affect pin state
affect pin state
1
Input (Pull-up
MOS off)
MOS off)
Pin state
Value is written to PJDR, but does not
affect pin state
affect pin state
(n = 0 to 7)