Renesas Stereo System SH7709S Manual De Usuario

Rev. 5.00, 09/03, page 614 of 760

Figure 20.1 shows a block diagram of the A/D converter.

10-bit

D/A

ADDRA

ADDRB

ADDRD

Bus interface

Peripheral data bus

Analog

multi-

plexer

Control circuit

Successive approxi-

mation register

+

−

Comparator

Sample-and-

hold circuit

ADI
interrupt
signal

AV

SS 

AN0 

AN1 

AN2 

AN3 

AN4 

AN5 

AN6 

AN7 

φ

/8

φ

/16

ADCSR

ADCR

AV

CC

A/D converter

ADCR: A/D control register

ADCSR: A/D control/status register

ADDRA: A/D data register A

ADDRB: A/D data register B

ADDRC: A/D data register C

ADDRD: A/D data register D

Legend

Internal

data bus

ADTRG

ADDRC