Renesas Stereo System SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 725 of 760
A.4
Pin States in Access to Each Address Space
Table A.3
Pin States (Ordinary Memory/Little Endian)
8-Bit Bus Width
16-Bit Bus Width
Pin
Byte/Word/Long-
word Access
Byte Access
(Address 2n)
Byte Access
(Address 2n + 1)
Word/Longword
Access
CS6
to
CS2
,
CS0
Enabled
Enabled
Enabled
Enabled
R
Low
Low
Low
Low
RD
W High
High
High
High
R
High
High
High
High
RD/
WR
W Low
Low
Low
Low
BS
Enabled
Enabled
Enabled
Enabled
RAS3U
/PTE[2]
High
High
High
High
RAS3L
/PTJ[0]
High
High
High
High
CASL
/PTJ[2]
High
High
High
High
CASU
/PTJ[3]
High
High
High
High
R
High
High
High
High
WE0
/DQMLL
W Low
Low
High
Low
R
High
High
High
High
WE1
/DQMLU/
WE
W High
High
Low
Low
R
High
High
High
High
WE2
/DQMUL/
ICIORD
/PTK[6]
W High
High
High
High
R
High
High
High
High
WE3
/DQMUU/
ICIOWR
/PTK[7]
W High
High
High
High
CE2A
/PTE[4]
High
High
High
High
CE2B
/PTE[5]
High
High
High
High
CKE/PTK[5]
Disabled
Disabled
Disabled
Disabled
WAIT
Enabled
*
1
Enabled
*
1
Enabled
*
1
Enabled
*
1
IOIS16
/PTG[7]
Disabled
Disabled
Disabled
Disabled
A25 to A0
Address
Address
Address
Address
D7 to D0
Valid data
Valid data
Invalid data
Valid data
D15 to D8
High-Z
*
2
Invalid data
Valid data
Valid data
D31 to D16
High-Z
*
2
High-Z
*
2
High-Z
*
2
High-Z
*
2