Maxim DS33R11 Manual De Usuario

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

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DTE and DCE Mode .............................................................................................................................58

MAC ........................................................................................................................... 59

MII Mode Options..................................................................................................................................61

RMII Mode.............................................................................................................................................61

PHY MII Management Block and MDIO Interface ................................................................................62

................................................................................................. 62

Receive Data Interface .........................................................................................................................63

Repetitive Pattern Synchronization.......................................................................................................64

Pattern Monitoring.................................................................................................................................64

Pattern Generation................................................................................................................................64

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INTEGRATED T1/E1/J1 TRANSCEIVER ........................................................................................ 72

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T1 Transmit Transparency....................................................................................................................74

AIS-CI and RAI-CI Generation and Detection ......................................................................................74

T1 Receive-Side Digital-Milliwatt Code Generation..............................................................................75

........................................................................... 76

Automatic Alarm Generation.................................................................................................................77

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Line-Code Violation Counter (TR.LCVCR) ...........................................................................................78

Path Code Violation Count Register (TR.PCVCR) ...............................................................................79

Frames Out-of-Sync Count Register (TR.FOSCR) ..............................................................................80

E-Bit Counter (TR.EBCR) .....................................................................................................................80

........................................................................................................ 81

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Processor-Based Receive Signaling ....................................................................................................82

Hardware-Based Receive Signaling .....................................................................................................83

Processor-Based Transmit Signaling ...................................................................................................84

Hardware-Based Transmit Signaling ....................................................................................................85

........................................................................................ 86

Idle-Code Programming Examples .......................................................................................................87

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Receive Elastic Store ............................................................................................................................88

Transmit Elastic Store ...........................................................................................................................89

Elastic Stores Initialization ....................................................................................................................89

Minimum Delay Mode ...........................................................................................................................89

)............................................................ 90

............................................................................... 91

Transmit BOC .......................................................................................................................................91

BOC .............................................................................................................................. 91

)........................................... 92

Method 1: Internal Register Scheme Based on Double-Frame............................................................92

Method 2: Internal Register Scheme Based on CRC4 Multiframe .......................................................92

....................................................... 93

HDLC Configuration ..............................................................................................................................93

FIFO Control .........................................................................................................................................95

HDLC Mapping......................................................................................................................................95