Cypress EZ-OTG CY7C67200 Manual De Usuario

Document #: 38-08014 Rev. *G

Page 58 of 78

CRC Enable (Bit 13)

The CRC Enable bit enables or disables the CRC operation.

1: Enables CRC operation

0: Disables CRC operation

CRC Clear (Bit 12)

The CRC Clear bit will clear the CRC with a load of all ones.
This bit is self clearing and always reads ‘0’.

1: Clear CRC with all ones

0: No Function

Receive CRC (Bit 11)

The Receive CRC bit determines whether the receive bit
stream or the transmit bit stream is used for the CRC data input
in full duplex mode. This bit is a don’t care in half-duplex mode.

1: Assigns the receive bit stream

0: Assigns the transmit bit stream

One in CRC (Bit 10)

The One in CRC bit is a read-only bit that indicates if the CRC
value is all zeros or not.

1: CRC value is not all zeros

0: CRC value is all zeros

Zero in CRC (Bit 9)

The Zero in CRC bit is a read-only bit that indicates if the CRC
value is all ones or not.

1: CRC value is not all ones

0: CRC value is all ones

All reserved bits must be written as ‘0’.

The SPI CRC Value register contains the CRC value.

CRC (Bits [15:0])

The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7]
are invalid in CRC7 mode.

The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO
byte mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to ‘1’ (RxIntVal triggers) or the Receive

CRC...

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

1

1

1

1

1

1

1

1

...CRC

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

1

1

1

1

1

1

1

1

Reserved

-

-

-

-

-

-

-

-

X

X

X

X

X

X

X

X

Data

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

X

X

X

X

X

X

X

X