Atmel SpaceWire Router SpW-10X Manual De Usuario
Ref.: UoD_SpW-10X_
UserManual
Issue: 3.4
SpW-10X
SpaceWire Router
User Manual
Date: 11
th
July 2008
Preliminary
10
I
LIST OF FIGURES
F
IGURE
2-1
S
TAND
-A
LONE
R
OUTER
...................................................................................................................... 16
F
IGURE
2-2
N
ODE
I
NTERFACE
................................................................................................................................ 17
F
IGURE
2-3
E
MBEDDED
R
OUTER
........................................................................................................................... 18
F
IGURE
2-4
E
XPANDING THE NUMBER OF
S
PACE
W
IRE
P
ORTS
(1) .......................................................................... 19
F
IGURE
2-5
E
XPANDING THE NUMBER OF
S
PACE
W
IRE
P
ORTS
(2) .......................................................................... 20
F
IGURE
3-1
S
PACE
W
IRE ROUTER BLOCK DIAGRAM
............................................................................................... 22
F
IGURE
5-1
LVDS
R
ECEIVER
F
AIL
-S
AFE
R
ESISTORS
............................................................................................ 35
F
IGURE
5-2
C
ONFIGURATION INTERFACE TIMING SPECIFICATION
.......................................................................... 42
F
IGURE
5-3
PLL
WITH EXTERNAL COMPONENTS
.................................................................................................... 46
F
IGURE
6-1
E
XTERNAL PORT WRITE TIMING SPECIFICATION
.................................................................................. 47
F
IGURE
6-2
E
XTERNAL PORT READ TIMING SPECIFICATION
.................................................................................... 48
F
IGURE
6-3
T
IME
-C
ODE
I
NPUT
I
NTERFACE
............................................................................................................ 48
F
IGURE
6-4
T
IME
-C
ODE
O
UTPUT
I
NTERFACE
........................................................................................................ 49
F
IGURE
6-5
T
IME
-
CODE RESET INTERFACE
............................................................................................................. 49
F
IGURE
6-6
S
TATUS
M
ULTIPLEXER OUTPUT INTERFACE
........................................................................................ 49
F
IGURE
6-7
R
ESET CONFIGURATION INTERFACE TIMING SPECIFICATION
................................................................ 51
F
IGURE
7-1
N
ORMAL ROUTER DATA PACKETS
....................................................................................................... 55
F
IGURE
7-2
C
OMMAND
P
ACKET
F
ORMAT
.............................................................................................................. 55
F
IGURE
7-3
R
EAD
S
INGLE
A
DDRESS
C
OMMAND
F
ORMAT
..................................................................................... 57
F
IGURE
7-4
R
EAD
S
INGLE
A
DDRESS
R
EPLY
P
ACKET
F
ORMAT
............................................................................... 59
F
IGURE
7-5
R
EAD
I
NCREMENTING
A
DDRESS
C
OMMAND
F
ORMAT
......................................................................... 62
F
IGURE
7-6
R
EAD
I
NCREMENTING
A
DDRESS
R
EPLY
P
ACKET
F
ORMAT
.................................................................. 64
F
IGURE
7-7
R
EAD
-M
ODIFY
-W
RITE
C
OMMAND
P
ACKET
F
ORMAT
......................................................................... 66
F
IGURE
7-8
R
EAD
-M
ODIFY
-W
RITE EXAMPLE OPERATION
..................................................................................... 68
F
IGURE
7-9
R
EAD
-M
ODIFY
-W
RITE
R
EPLY
P
ACKET
F
ORMAT
................................................................................ 69
F
IGURE
7-10
W
RITE
S
INGLE
A
DDRESS
C
OMMAND
P
ACKET
................................................................................... 71
F
IGURE
7-11
W
RITE
S
INGLE
A
DDRESS
R
EPLY
P
ACKET
......................................................................................... 73
F
IGURE
7-12
S
OURCE
P
ATH
A
DDRESS FIELD DECODING
........................................................................................ 78
F
IGURE
7-13
S
OURCE
P
ATH
A
DDRESSES IN
R
EPLY
P
ACKET
.................................................................................. 78
F
IGURE
7-14
N
ORMAL
C
ONFIGURATION
P
ACKET
H
EADER
S
TRUCTURE
................................................................ 78
F
IGURE
7-15
F
ILL
B
YTES
C
ONFIGURATION
H
EADER
S
TRUCTURE
.......................................................................... 78
F
IGURE
8-1
D
EACTIVATE DRIVER OPERATING MODE
............................................................................................. 81
F
IGURE
8-2
D
EACTIVATED
LDVS
DRIVER OUTPUT
................................................................................................ 81
F
IGURE
8-3
D
EACTIVATED
LDVS
DRIVER OUTPUT CONNECTED TO EXTERNAL BIAS NETWORK ON
LVDS
INPUT
.. 82
F
IGURE
8-4
S
TART ON
R
EQUEST MODE
.................................................................................................................. 85
F
IGURE
8-5
D
ISABLE ON
S
ILENCE MODE
................................................................................................................ 86
F
IGURE
8-6
A
RBITRATION OF TWO PACKETS WITH MATCHING PRIORITY
. .............................................................. 87
F
IGURE
8-7
A
RBITRATION OF THREE PACKETS WITH MATCHING PRIORITY
............................................................ 88