Delta Tau GEO BRICK LV Manual De Usuario
Turbo PMAC User Manual
Turbo PMAC General Purpose I/O Use
205
Setup Register 3: Latch Control
Setup Register 3 at each address {Base + 0} through {Base + 5}, which is selected by writing a 1 to Bit 6
of the Control Word at {Base + 7} and a 1 to Bit 7, is the latch control register for the Data Register at the
same address. Each bit of Setup Register 3 controls whether latched or unlatched data is read from the
matching bit of the Data Register at the same address.
Setup Register 3 at each address {Base + 0} through {Base + 5}, which is selected by writing a 1 to Bit 6
of the Control Word at {Base + 7} and a 1 to Bit 7, is the latch control register for the Data Register at the
same address. Each bit of Setup Register 3 controls whether latched or unlatched data is read from the
matching bit of the Data Register at the same address.
A value of 0 in the bit of Setup Register 3 selects unlatched data to be read from the matching bit of the
Data Register at the same address; a value of 1 in the bit selects latched data to be read.
Data Register at the same address; a value of 1 in the bit selects latched data to be read.
For both the latched and unlatched settings, the matching bit of Setup Register 2 controls exactly what
type of data is read from the Data Register.
type of data is read from the Data Register.
Data Registers
The Data Register at each address {Base + 0} through {Base + 5}, which is selected by writing a 0 to Bit
6 of the Control Register at {Base + 7} and a 0 to Bit 7, provides the working interface for the 8
input/output lines matched to that address. The processor reads from or writes to the data register to
access the input/output lines.
6 of the Control Register at {Base + 7} and a 0 to Bit 7, provides the working interface for the 8
input/output lines matched to that address. The processor reads from or writes to the data register to
access the input/output lines.
If there is a value of 1 in Bit n (n = 0 to 5) of the Control Word, a write operation to the Data Register at
address {Base + n} has no effect on the I/O line, effectively disabling the output function for all 8 lines
associated with the register.
address {Base + n} has no effect on the I/O line, effectively disabling the output function for all 8 lines
associated with the register.
A read operation from a Data Register can access one of 4 types of data for each I/O line associated with
the register (individually selectable), depending on how the Setup Registers 2 and 3 at the same address
have been configured.
the register (individually selectable), depending on how the Setup Registers 2 and 3 at the same address
have been configured.
The following table summarizes how the Setup Register bits control what data is read in the matching bit
of the Data Register:
of the Data Register:
Setup Register 3 Bit Value
Setup Register 2 Bit Value
Data Type Read
0 0
Pin
Value
Read
0
1
Writeable Register Read
1 0
Latched
Input
Read
1
1
Converted Gray Code Read
Pin Data Read
If the pin value has been selected to be read, the line voltages for the eight I/O lines is read as an input,
even if it is being driven as an output.
If the pin value has been selected to be read, the line voltages for the eight I/O lines is read as an input,
even if it is being driven as an output.
Writeable Register Data Read
If the writeable register value has been selected to be read, the value written by the processor into the data
register is read back, even if this does not match the voltage state of the pin.
If the writeable register value has been selected to be read, the value written by the processor into the data
register is read back, even if this does not match the voltage state of the pin.
Latched Input Read
If the latched input has been selected to be read, the input value last latched by the falling edge of line En
for address {Base + n} is read, even if the input value has changed since then.
If the latched input has been selected to be read, the input value last latched by the falling edge of line En
for address {Base + n} is read, even if the input value has changed since then.
Converted Gray Code Read
If the converted Gray code input has been selected to be read, the input value last latched by line En for
address {Base + n} and processed through the Gray code conversion circuitry is read.
If the converted Gray code input has been selected to be read, the input value last latched by line En for
address {Base + n} and processed through the Gray code conversion circuitry is read.