Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 Manual De Usuario
Los códigos de productos
BX80605X3430
Processor Integrated I/O (IIO) Configuration Registers
130
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.4.5.17
IR[16:17]—Increment Registers 16-17
3.4.5.18
IR[18:23]—Increment Registers 18-23
Register:
IR[16:17]
Device:
8
Function: 1
Offset:
180h-184h by 4
Bit
Attr
Default
Description
31:0
RWLB
0h
Increment
These registers are physically mapped to scratch pad registers. A read from IR[n]
These registers are physically mapped to scratch pad registers. A read from IR[n]
reads SR[n] and then increments SR[n]. A write to IR[n] increments SR[n] while
the write data is unused. Increments within SR[n] for reads and writes roll over to
zero. The read or write and the increment side effect are atomic with respect to
other accesses. The registers provide firmware with synchronization variables
(semaphores) that are overloaded onto the same physical registers as SR.
Register:
IR[18:23]
Device:
8
Function: 1
Offset:
188h-19Ch by 4
Bit
Attr
Default
Description
31:0
RW
0h
Increment
These registers are physically mapped to scratch pad registers. A read from IR[n]
These registers are physically mapped to scratch pad registers. A read from IR[n]
reads SR[n] and then increments SR[n]. A write to IR[n] increments SR[n] while
the write data is unused. Increments within SR[n] for reads and writes roll over to
zero. The read or write and the increment side effect are atomic with respect to
other accesses. The registers provide firmware with synchronization variables
(semaphores) that are overloaded onto the same physical registers as SR.